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[ak4373] ms0991-e-00 2008/09 - 1 - general description the ak4373 is a low power stereo 24bit dac wi th an integrated stereo headphone amplifier and a monaural speaker driver. it can be used for a variet y of portable audio and medi a player applications, including game consoles, dedicat ed headphone drivers, personal navigat ion devices, and portable media players. the output drivers can be configured for three unique use ca ses: mono speaker driver or single-ended ac-coupled headphones wh ich can be used as ster eo line-out, dc-coupled btl headphones and pseudo cap-less. the ak4373 operates off of a low-voltage power supply, ranging from 2.2v to 3.6v. the output amplifiers operat e at up to 4.0v of the headphone power supply. the device is packaged in a space-savi ng 32-pin qfn package. features ? sampling rate: 8 khz 48 khz ? 8-times over sampling digital filter ? scf with high tolerance to clock jitter ? stereo headphone amplifier 65mw output (single-ended mode) into 16 ? 3.3v snr: 96db 130mw output (differential mode) into 32 ? 3.3v snr: 96db 60mw output (pseudo cap-less mode) into 16 ? 3.3v snr: 86db pop-noise free at power-up and reset ? stereo lineout snr: 96db ? mono speaker driver available for both dynamic and piezo speaker 0.8w @ 8 ? hvdd = 4.0v 1.0w @ 4 ? hvdd = 4.0v snr: 97db ? digital processing hpf, lpf, 3d enhance, freque ncy compensation, 5-biquads, digital alc/limiter: +36d b to -54db, 0.375db/step ? digital volume control: +12db to -115db, 0.5db/step, mute ? analog mixing: mono input ? pll: input frequency: 27mhz, 25mhz, 24mhz, 13.5mhz, 12.288mhz, 12mhz, and 11.2896mhz (mcki pin) 1fs (lrck pin) 32fs or 64fs (bick pin) input level: cmos or ac coupling input ? master clock (m cki pin): 256/512/1024fs ? master clock output (mcko pin): 32fs, 64fs, 128fs, 256fs ? p interface: 3-wire serial, i 2 c bus (version1.0, 400 khz fast-mode) ? audio interface format: msb first, 2?s complement 16/20/24bit msb justified, 16/20/24bit lsb justified, 16/20/24bit i 2 s, 16/20/24bit dsp mode ? cmos input level low power stereo dac with hp/spk-amp ak4373
[ak4373] ms0991-e-00 2008/09 - 2 - ? power supply: analog (avdd): 2.2 to 3.6v digital (dvdd): 1.6 to 3.6v driver (hvdd): 2.2 to 4.0v ? power consumption: 11.9mw headphone playback ? ta = -30 ~ +85 c ? package: 32-pin qfn (5mm x 5mm, 0.5mm pitch) ? pin/register compatible with ak4343 block diagram d/a datt smute pmdac pmhpl pmhpr stereo line out headphone digital processing - hpf - lpf - 3d enhance - frequency compensation - 5-biquads - alc/limiter hpl hp r mutet hvdd vss2 avdd vss1 vcom dvdd lout rout mono in min- pmspk speaker spp spn vss3 audio i/f pll pmpll pdn bick lrck sdti mcki vcoc control register scl/cclk sda/cdti mcko cad0/csn i2c pmmin min+ dach dach dacs mins minh vol hpg vol hpg vol spkg [ 1:0 ] figure 1. block diagram (single-ended mode, hpbtl bit =pseudo bit = ?0?)
[ak4373] ms0991-e-00 2008/09 - 3 - mutet hvdd vss2 avdd vss1 vcom dvdd pmhpr hpr+ hpr- vss3 pdn control register scl/cclk sda/cdti cad0/csn i2c headphone(rch) d/a datt smute pmdac digital processing - hpf - lpf - 3d enhance - frequency compensation - 5-biquads - alc/limiter pmhpl hpl+ hpl- headphone(lch) audio i/f pll pmpll pdn bick lrck sdti mcki vcoc mcko mono in min- pmmin min+ dach minh dach vol hpg vol hpg figure 2. block diagram (differential m ode, hpbtl bit = ?1?, pseudo bit = ?0?) d/a datt smute pmdac pmhpl pmhpr headphone digital processing - hpf - lpf - 3d enhance - frequency compensation - 5-biquads - alc/limiter hpl hpr mutet hvdd vss2 avdd vss1 vcom dvdd mono in min- hvcm vss3 audio i/f pll pmpll pdn bick lrck sdti mcki vcoc control register scl/cclk sda/cdti mcko cad0/csn i2c pmmin min+ common pmhpl or pmhpr test dach minh dach vol hpg vol hpg figure 3. block diagram (pseudo cap-less mode, hpbtl bit = ?0?, pseudo bit = ?1?)
[ak4373] ms0991-e-00 2008/09 - 4 - ordering guide ak4373en ? 30 +85 c 32pin qfn (0.5mm pitch) AKD4373 evaluation board for ak4373 pin layout mutet rout lout min+ min- nc nc nc hpl / hpl+ hpr / hpl- vss2 hvdd spp / hpr+ / test spn / hpr- / hvcm mcko mcki nc vcom vss1 avdd vcoc i2c pdn csn / cad0 vss3 dvdd bick lrck nc sdti cdti / sda cclk / scl ak4373en top view 25 26 27 28 29 30 31 32 1 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 2 3 4 5 6 7 8
[ak4373] ms0991-e-00 2008/09 - 5 - comparison table between ak4343 and ak4373 1. function function ak4343 ak4373 dac resolution 16bit 24bit hp-amp s/n 90db 96db(single), 96db(btl) hp-amp output type single-ended single-ended, differential or pseudo cap-less five programmable biquads no yes line output pins independent from hp/spk shared with hpl/hpr mcki input level cmos cmos or 0.4vpp ac coupling analog mixing 3-stereo 1-mono (single/differential) receiver amp yes no spk amp 1.2w@8 ? , 5v 1.0w@4 ? , 4.0v 2. pin pin# ak4343 ak4373 1 test1 nc 3 avss vss1 5 vcoc / rin3 vcoc 12 test2 nc 16 dvss vss3 19 spn spn / hpr ? / hvcm 20 spp spp / hpr+ / test 22 hvss vss2 23 hpr hpr / hpl ? 24 hpl hpl / hpl+ 28 min / lin3 min+ 29 rin2 / in2 ? min- 30 lin2 / in2+ nc 31 lin1 / in1 ? nc 32 rin1 / in1+ nc
[ak4373] ms0991-e-00 2008/09 - 6 - 3. register addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmmin pmspk pmlo pmdac 0 0 01h power management 2 0 hpmtn pmhpl pmhpr m/s mckac mcko pmpll 02h signal select 1 sppsn mins dacs dacl hpbtl pmmp pseudo mgain0 03h signal select 2 lovl lops mgain1 spkg1 spkg0 minl 0 0 04h mode control 1 pll3 pll2 pll1 pll0 bcko dif2 dif1 dif0 05h mode control 2 ps1 ps0 fs3 msbs bckp fs2 fs1 fs0 06h timer select dvtm wtm2 ztm1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control avl 7 avl6 avl5 avl4 avl 3 avl2 avl1 avl0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0bh alc mode control 3 rgain1 lmth1 0 0 0 frn vbat 0 0ch rch input volume control avr7 avr6 avr5 avr4 avr3 avr2 avr1 avr0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 0eh mode control 3 0 0 smute dvolc bst1 bst0 dem1 dem0 0fh mode control 4 0 0 0 0 avolc hpm minh dach 10h power management 3 inr1 inl1 hpg mdif2 mdif 1 inr0 inl0 0 11h digital filter select 1 gn1 gn0 lpf hpf eq fil3 0 0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h reserved 0 0 pmainr3 pmainl3 pmainr2 pmainl2 pmmicr pmmicl 21h reserved 0 0 micr3 micl3 0 0 ain3 rcv 22h reserved 0 0 0 0 rinr3 linl3 rinr2 linl2 23h reserved 0 0 0 0 rinh3 linh3 rinh2 linh2 24h reserved 0 0 0 0 rins3 lins3 rins2 lins2 25h reserved 0 0 0 0 0 0 0 0 26h reserved 0 0 0 0 0 0 0 0 27h reserved 0 0 0 0 0 0 0 0 28h reserved 0 0 0 0 0 0 0 0 29h reserved 0 0 0 0 0 0 0 0 2ah reserved 0 0 0 0 0 0 0 0 2bh reserved 0 0 0 0 0 0 0 0 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8 these bits were added to the ak4373. these bits were removed from the ak4343. these bits name were changed.
[ak4373] ms0991-e-00 2008/09 - 7 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 31h reserved 0 0 0 0 0 0 0 0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 these bits were added to the ak4373. these bits were removed from the ak4343.
[ak4373] ms0991-e-00 2008/09 - 8 - pin/function no. pin name i/o function 1 nc - no connect pin no internal bonding. this pin should be open or connected to the ground. 2 vcom o common voltage output pin, 0.5 x avdd bias voltage of dac outputs. 3 vss1 - analog ground pin 4 avdd - analog power supply pin 2.2 3.6v 5 vcoc o output pin for loop filter of pll circuit this pin must be connected to vss1 with one resistor and capacitor in series. 6 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial 7 pdn i power-down mode pin ?h?: power-up, ?l?: power-down, reset and initialization of the control register. the ak4373 must be reset once upon power-up. csn i chip select pin (i2c pin = ?l?: 3-wire serial mode) 8 cad0 i chip address 1 select pin (i2c pin = ?h?: i 2 c bus mode) cclk i control data clock pin (i2c pin = ?l?: 3-wire serial mode) 9 scl i control data clock pin (i2c pin = ?h?: i 2 c bus mode) cdti i control data input pin (i2c pin = ?l?: 3-wire serial mode) 10 sda i/o control data input pin (i2c pin = ?h?: i 2 c bus mode) 11 sdti i audio serial data input pin 12 nc - no connect pin no internal bonding. this pin should be open or connected to the ground. 13 lrck i/o input / output channel clock pin 14 bick i/o audio serial data clock pin 15 dvdd - digital power supply pin. 1.6 3.6v 16 vss3 - digital ground pin 17 mcki i external master clock input pin 18 mcko o master clock output pin
[ak4373] ms0991-e-00 2008/09 - 9 - no. pin name i/o function spn o speaker amp negative output pin single-ended mode (hpbtl bit = pseudo bit = ?0?) hpr ? o rch headphone-amp negative output pin differential mode (hpbtl bit = ?1?, pseudo bit = ?0?) 19 hvcm o common output voltage for headphone-amp pin pseudo cap-less mode (hpbtl bit = ?0?, pseudo bit = ?1?) spp o speaker amp positive output pin single-ended mode (hpbtl bit = pseudo bit = ?0?) hpr+ o rch headphone-amp positive output pin differential mode (hpbtl bit = ?1?, pseudo bit = ?0?) 20 test o this pin must be open. pseudo cap-less mode (hpbtl bit = ?0?, pseudo bit = ?1?) 21 hvdd - headphone & speaker amp power supply pin. 2.2 4.0v 22 vss2 - headphone & speaker amp ground pin hpr o rch headphone-amp output pin single-ended mode (hpbtl bit = pseudo bit = ?0?) pseudo cap-less mode (hpbtl bit = ?0?, pseudo bit = ?1?) 23 hpl ? o lch headphone-amp negative output pin differential mode (hpbtl bit = ?1?, pseudo bit = ?0?) hpl o lch headphone-amp output pin single-ended mode (hpbtl bit = pseudo bit = ?0?) pseudo cap-less mode (hpbtl bit = ?0?, pseudo bit = ?1?) 24 hpl+ o lch headphone-amp positive output pin differential mode (hpbtl bit = ?1?, pseudo bit = ?0?) 25 mutet o mute time constant control pin connected to the vss2 pin with a capacitor for mute time constant. 26 rout o rch line output pin this pin is internal connected to the hpr pin. 27 lout o lch line output pin this pin is internal connected to the hpl pin. 28 min+ i mono signal positive input (differential i nput) or mono signal i nput (single-ended input) 29 min- i mono signal negative input (differential input) if the min+ pin is used as single-ended, this pin should be connected to the vss1 with a capacitor. 30 nc - no connect pin no internal bonding. this pin should be open or connected to the ground. 31 nc - no connect pin no internal bonding. this pin should be open or connected to the ground. 32 nc - no connect pin no internal bonding. this pin should be open or connected to the ground. note 1. all input pins must not be left floating. note 2. dvdd or vss3 voltage must be input to i2c pin. note 3. all analog input pins (min+/- pins) must be supplied signal via ac-coupling capacitor. note 4. analog output pins (hpl, hpr, lout, and rout pins) must deliver signal via ac-coupling capacitor except speaker output (spp, spn pins) and headphone output in differential mode (hpl+/- and hpr+/- pins) and headphone output in pseudo cap-le ss mode (hpl and hpr pins).
[ak4373] ms0991-e-00 2008/09 - 10 - handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog vcoc, spn/hpr ? /hvcm, spp/hpr+/test, hpr/hpl-, hpl/hpl+, min+, min-, mutet these pins must be open. mcko this pin must be open. digital mcki this pin must be connected to vss3. absolute maximum ratings (vss1=vss2=vss3=0v; note 5 ) parameter symbol min max units power supplies: analog avdd ? 0.3 4.6 v digital dvdd ? 0.3 4.6 v headphone-amp / speaker-amp hvdd ? 0.3 4.6 v input current, any pin except supplies iin - 10 ma analog input voltage ( note 7 ) vina ? 0.3 (avdd+0.3) or 4.6 v digital input voltage ( note 8 ) vind ? 0.3 (dvdd+0.3) or 4.6 v ambient temperature (powered applied) ta ? 30 85 c storage temperature tstg ? 65 150 c maximum power dissipation ( note 9 ) pd - 511 mw note 5. all voltages are with respect to ground. note 6. vss1, vss2 and vss3 must be connected to the same analog ground plane. note 7. i2c, min+, min- pin note 8. pdn, csn/cad0, cclk/scl, cd ti/sda, sdti, lrck, bick, mcki pins pull-up resistors at sda and sc l pins must be connected to (dvdd+0.3)v or less voltage. note 9. in case that the exposed pad is connected to the ground and pcb drawing density is 100%.this power is the ak4373 internal dissipation that does not include power of externally connected speaker and headphone. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss1=vss2=vss3=0v; note 5 ) parameter symbol min typ max units power supplies analog avdd 2.2 3.3 3.6 v ( note 10 ) digital dvdd 1.6 3.3 3.6 v hp / spk-amp hvdd 2.2 3.3 4.0 v difference1 dvdd ? avdd - - +0.3 v difference2 dvdd ? hvdd - - +0.3 v note 5. all voltages are with respect to ground. note 10. the power-up sequence between avdd, dvdd and hvdd is not critical. when only avdd or hvdd is powered off, the power supply current of dvdd at power-down mode may be increased. dvdd must not be powered off while avdd or hvdd is powered on. * akemd assumes no responsibility for the usag e beyond the conditions in this datasheet.
[ak4373] ms0991-e-00 2008/09 - 11 - analog characteristics (ta=25 c; avdd=dvdd=hvdd=3.3v; vss1=vss2=vss3=0 v; fs=44.1khz, bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units dac characteristics: resolution - - 24 bits stereo line output characteristics: dac lout/rout pins, single-ended mode ( figure 4 ), hpbtl bit = ?0?, pseudo bit = ?0?, hpg bit = ?0?, hvdd=3.3v, c=1 f, r l =10k , alc=off, avol=0db, dvol=0db; unless otherwise specified. output voltage (0dbfs) ( note 11 ) 1.78 1.98 2.18 vpp s/(n+d) (0dbfs) - 77 - db s/n (a-weighted) 86 96 - db interchannel isolation 60 80 - db load resistance rl 10 - - k load capacitance c1 - - 30 pf note 11. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ). lout/rout pin line-amp c rl measurement point c1 figure 4. line-amp output circuit parameter min typ max units headphone-amp characteristics: dac hpl/hpr pins, single-ended mode ( figure 5 ), hpbtl bit = ?0?, pseudo bit = ?0?, hpg bit = ?0?, hvdd=3.3v, c=47f, r l =22.8 ? , alc=off, avol=0db, dvol=0db; unless otherwise specified. output voltage ( note 12 ) 0dbfs 1.58 1.98 2.38 vpp 0dbfs ( note 13 ) - 3.00 - vpp 0dbfs ( note 14 ) - 1.02 - vrms s/(n+d) ? 3dbfs 50 60 - db ? 3dbfs ( note 13 ) - 65 - db 0dbfs ( note 14 ) - 20 - db 86 96 - db s/n (a-weighted) ( note 13 ) - 96 - db interchannel isolation 60 75 - db interchannel gain mismatch - 0 0.8 db load resistance r l =r1+r2 16 - - load capacitance c1 - - 30 pf c2 - - 300 pf note 12. output voltage is proportional to avdd voltage. vout = 0.6 x avdd(typ)@hpg bit = ?0 ?, 0.91 x avdd(typ)@hpg bit = ?1?. note 13. hpg bit = ?1?, hvdd=3.8v, c=47 f, r l =100 . note 14. hpg bit = ?1?, hvdd=3.3v, c=47 f, r l =16 .
[ak4373] ms0991-e-00 2008/09 - 12 - hpl/hpr pin hp-amp c r2 measurement point c1 c2 r1 figure 5. hp-amp output circuit in single-ended mode parameter min typ max units headphone-amp characteristics: dac hpl+/-, hpr+/- pins, differential mode( figure 6 ), hpbtl bit = ?1?, pseudo bit = ?0? , hpg bit = ?0?, hvdd=3.3v, r l =32 , alc=off, avol=0db, dvol=0db; unless otherwise specified. output voltage ( note 15 ) 0dbfs - 3.96 - vpp 0dbfs ( note 16 ) - 2.05 - vrms s/(n+d) ? 3dbfs - 60 - db 0dbfs ( note 16 ) - 20 - db s/n (a-weighted) - 96 - db interchannel isolation - 75 - db interchannel gain mismatch - 0.2 - db load resistance r l =2 x r1 + r2 16 - - load capacitance c1 - - 30 pf c2 - - 300 pf note 15. output voltage is proportional to avdd voltage. vout = 1.2 x avdd(typ)@hpg bit = ?0 ?, 1.82 x avdd(typ)@hpg bit = ?1?. note 16. hpg bit = ?1?, hvdd=3.3v, r l =32 . hpl+/hpr+ pin hp-amp c1 c2 hpl-/hpr- pin c2 r2 hp-amp measurement point c1 r1 r1 figure 6. hp-amp output circuit in differential mode
[ak4373] ms0991-e-00 2008/09 - 13 - parameter min typ max units headphone-amp characteristics: dac hpl/hpr pins, pseudo cap-less mode( figure 7 ), hpbtl bit = ?0?, pseudo bit = ?1? , hpg bit = ?0?, hvdd=3.3v, r l =22.8 , alc=off, avol=0db, dvol=0db; unless otherwise specified. output voltage ( note 17 ) 0dbfs - 1.98 - vpp 0dbfs ( note 18 ) - 0.98 - vrms s/(n+d) ? 3dbfs - 38 - db 0dbfs ( note 18 ) - 20 - db s/n (a-weighted) - 86 - db interchannel isolation - 38 - db interchannel gain mismatch - 0 - db load resistance r l = r1 + r2 16 - - load capacitance c1 - - 30 pf c2 - - 300 pf note 17. output voltage is proportional to avdd voltage. vout = 0.6 x avdd(typ)@hpg bit = ?0 ?, 0.91 x avdd(typ)@hpg bit = ?1?. note 18. hpg bit = ?1?, hvdd=3.3v, r l =16 . hpl/hpr pin hp-amp c1 c2 hvcm pin vcom amp for hp-amp r2 measurement point c1 r1 note: impedance between headphone and the hvcm pin mu st be as low as possible. if the impedance is larger, crosstalk and distortion might be degraded. figure 7. hp-amp output circuit in pseudo cap-less mode
[ak4373] ms0991-e-00 2008/09 - 14 - parameter min typ max units speaker-amp characteristics: dac spp/spn pins, alc=off, avol=0db, dvol=0db, r l =8 , btl, hvdd=3.3v; unless otherwise specified. output voltage ( note 19 ) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 3.11 - vpp spkg1-0 bits = ?01?, ? 0.5dbfs (po=240mw) 3.13 3.92 4.71 vpp spkg1-0 bits = ?10?, ? 0.5dbfs (po=400mw) 2.04 vrms s/(n+d) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 50 - db spkg1-0 bits = ?01?, ? 0.5dbfs (po=240mw) 20 50 - db spkg1-0 bits = ?10?, ? 0.5dbfs (po=400mw) 20 db s/n (a-weighted) 87 97 - db load resistance 8 - - load capacitance - - 30 pf speaker-amp characteristics: dac spp/spn pins, alc=off, avol=0db, dvol=0db, c l =3 f, r series =20 x 2, btl, hvdd=3.8v; unless ot herwise specified. ( figure 53) output voltage ( note 19 ) spkg1-0 bits = ?10?, -0.5dbfs - 6.37 - vpp s/(n+d) ( note 20 ) spkg1-0 bits = ?10?, -0.5dbfs - 58 - db s/n (a-weighted) 97 - db load resistance ( note 21 ) 50 - - load capacitance ( note 21 ) - - 3 f mono input: min+ pin (external input resistance=20k ) single-ended input min- pin is connected to vss1 via input capacitor. maximum input voltage ( note 22 ) - 1.98 - vpp gain ( note 23 ) min+ ? hpl/hpr hpbtl bit = ?0? hpg bit = ?0? - 0 - db min+ ? hpl/hpr hpbtl bit = ?0? hpg bit = ?1? - +3.6 - db min+ ? hpl+/-, hpr+/- hpbtl bit = ?1? hpg bit = ?0? - +6 - db min+ ? hpl+/-, hpr+/- hpbtl bit = ?1? hpg bit = ?1? - +9.6 - db min ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? -0.07 +4.43 +8.93 db alc bit = ?0?, spkg1-0 bits = ?01? - +6.43 - db alc bit = ?0?, spkg1-0 bits = ?10? - +10.65 - db alc bit = ?0?, spkg1-0 bits = ?11? - +12.65 - db alc bit = ?1?, spkg1-0 bits = ?00? - +6.43 - db alc bit = ?1?, spkg1-0 bits = ?01? - +8.43 - db alc bit = ?1?, spkg1-0 bits = ?10? - +12.65 - db alc bit = ?1?, spkg1-0 bits = ?11? - +14.65 - db
[ak4373] ms0991-e-00 2008/09 - 15 - mono input: min+/min- pins (external input resistance=20k ) differential input maximum input voltage ( note 24 ) - 1.98 - vpp gain ( note 23 ) min+/- ? hpl/hpr hpbtl bit = ?0? hpg bit = ?0? - 0 - db min+/- ? hpl/hpr hpbtl bit = ?0? hpg bit = ?1? - +3.6 - db min+/- ? hpl+/-, hpr+/- hpbtl bit = ?1? hpg bit = ?0? - +6 - db min+/- ? hpl+/-, hpr+/- hpbtl bit = ?1? hpg bit = ?1? - +9.6 - db min+/min- ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? -0.07 +4.43 +8.93 db alc bit = ?0?, spkg1-0 bits = ?01? - +6.43 - db alc bit = ?0?, spkg1-0 bits = ?10? - +10.65 - db alc bit = ?0?, spkg1-0 bits = ?11? - +12.65 - db alc bit = ?1?, spkg1-0 bits = ?00? - +6.43 - db alc bit = ?1?, spkg1-0 bits = ?01? - +8.43 - db alc bit = ?1?, spkg1-0 bits = ?10? - +12.65 - db alc bit = ?1?, spkg1-0 bits = ?11? - +14.65 - db note 19. output voltage is proportional to avdd voltage. vout = 1.00 x avdd(typ)@spkg1-0 bits = ?00?, 1.25 x avdd(typ)@spkg1-0 bits = ?01?, 2.04 x avdd(typ)@spkg1-0 bits = ?10?, 2.57 x avdd(typ)@ spkg1-0 bits = ?11? at differential output. note 20. in case of measuring at spp and spn pins. note 21. load impedance is total impedance of series resistance (r series ) and piezo speaker impedance at 1khz in figure 56 . load capacitance is capacita nce of piezo speaker. when piezo speaker is used, 20 or more series resistors should be connected at both spp and spn pins, respectively. note 22. maximum voltage is in proportion to both avdd and external input resistance (rin). vin = 0.6 x avdd x 20k (typ)/rin. note 23. the gain is in inverse proportional to external resistance. note 24. the maximum voltage is in proportion to both avdd and external input resistance (rin). vin = (min+) ? (min-) = 0.6 x avdd x 20k (typ)/rin. the signals with same amplitude and inverted phase s hould be input to min+ and min- pins, respectively.
[ak4373] ms0991-e-00 2008/09 - 16 - parameter min typ max units power supplies: power-up (pdn pin = ?h?) all circuit power-up: avdd+dvdd ( note 25 ) - 7.8 - ma avdd+dvdd ( note 26 ) - 8.1 12 ma hvdd: hp-amp normal operation no output ( note 27 ) - 2.2 4 ma hvdd: spk-amp normal operation no output ( note 28 ) - 4.1 12 ma power-down (pdn pin = ?l?) ( note 29 ) avdd+dvdd+hvdd - 1 20 a note 25. pll master mode (mcki=12.288mhz) and pmdac = pmhpl = pmhpr = pmvcm = pmpll = mcko = m/s bits = ?1?, pmmin bit = ?0?. avdd=3.9ma(typ), dvdd=3.9ma(typ). ext slave mode (pmpll = m/s = mcko bits = ?0?): avdd=3.1ma(typ), dvdd=2.7ma(typ). note 26. pll master mode (mcki=12.288mhz) and pmdac = pmhpl = pmhpr = pmvcm = pmpll = mcko = m/s bits = ?1?, pmmin bit = ?1?. avdd=4.2ma(typ), dvdd=3.9ma(typ). ext slave mode (pmpll = m/s = mcko bits = ?0?): avdd=3.5ma(typ), dvdd=2.7ma(typ). note 27. pmdac = pmhpl = pmhpr = pmvcm = pmp ll = pmmin bits = ?1? and pmspk bit = ?0?. note 28. pmdac = pmspk = pmvcm = pmpll = pmmi n bits = ?1? and pmhpl = pmhpr bits = ?0?. note 29. all digital input pins are fixed to dvdd or vss3. power consumption for each operation mode common conditions: ta=25 c; vss1=vss2=vss3=0v; fs=44.1khz, external slave mode, bick=64fs; 1khz, 0dbfs input; (pmmin bit = ?0? )headphone & speaker = no output power management bit 00h 01h typical current avdd dvdd hvdd total power mode pmvcm pmmin pmspk pmdac pmhpl pmhpr [v] [ma] [v] [ma] [v] [ma] [mw] all power-down 0 0 0 0 0 0 3.3 0 3.3 0 3.3 0 0 2.2 1.9 11.9 2.2 2.7 1.8 1.0 4.0 2.6 18.1 dac ? hp/line out 1 0 0 1 1 1 3.3 3.1 3.3 2.7 3.3 2.2 26.4 2.2 4.2 17.0 2.2 2.7 1.8 1.0 4.0 5.2 28.5 dac ? spk 1 0 1 1 0 0 3.3 3.2 3.3 2.7 3.3 4.1 33.0 table 1. power consumption for each operation mode (typ)
[ak4373] ms0991-e-00 2008/09 - 17 - filter characteristics (ta=-30 ~ 85 c; avdd=2.2 3.6v, dvdd=1.6 3.6v; hvdd=2.2 4.0v; fs=44.1khz; dem=off; hpf=lpf=fil3=eq=5-biquads=alc=off) parameter symbol min typ max units dac digital filter (lpf): passband ( note 30 ) -0.05db pb 0 - 20.0 khz ? 6.0db - 22.05 - khz stopband sb 24.1 - - khz passband ripple pr - - 0.02 db stopband attenuation sa 54 - - db group delay ( note 31 ) gd - 25 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 1.0 - db note 30. the passband and stopband frequencies scale with fs (system sampling rate). for example, pb=0.454*fs (@ ? 0.05db). each response refers to that of 1khz. note 31. the calculated delay time caused by digital filtering. this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. hpf=lpf=fil3=eq=5-biquads=alc=off. dc characteristics (ta=-30 ~ 85 c; avdd=2.2 3.6v, dvdd=1.6 3.6v; hvdd=2.2 4.0v) parameter symbol min typ max units high-level input voltage 2.2v dvdd 3.6v vih 70 % dvdd - - v 1.6v dvdd<2.2v vih 80 % dvdd - - v low-level input voltage 2.2v dvdd 3.6v vil - - 30 % dvdd v 1.6v dvdd<2.2v vil - - 20 % dvdd v input voltage at ac coupling ( note 32 ) vac 0.4 - - vpp high-level output voltage (iout = ? 200 a) voh dvdd ? 0.2 - - v low-level output voltage (except sda pin: iout = 200 a) vol - - 0.2 v (sda pin, 2.0v dvdd 3.6v: iout = 3ma) vol - - 0.4 v (sda pin, 1.6v dvdd<2.0v: iout = 3ma) vol - - 20%dvdd v input leakage current iin - - 10 a note 32. mcki is connected to a capacitor. ( figure 8 )
[ak4373] ms0991-e-00 2008/09 - 18 - switching characteristics (ta=-30 ~ 85 c; avdd=2.2 3.6v, dvdd=1.6 3.6v; hvdd=2.2 4.0v;c l =20pf; unless otherwise specified) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns ac pulse width tacw 18.5 - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns
[ak4373] ms0991-e-00 2008/09 - 19 - parameter symbol min typ max units pll slave mode (pll reference clock = lrck pin) lrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns pll slave mode (pll reference clock = bick pin) lrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - %
[ak4373] ms0991-e-00 2008/09 - 20 - parameter symbol min typ max units audio interface timing (dsp mode) master mode lrck ? ? to bick ? ? ( note 33 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns lrck ? ? to bick ? ? ( note 34 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck ? ? to bick ? ? ( note 33 ) tlrb 0.4 x tbck - - ns lrck ? ? to bick ? ? ( note 34 ) tlrb 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 33 ) tblr 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 34 ) tblr 0.4 x tbck - - ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns audio interface timing (r ight/left justified & i 2 s) master mode bick ? ? to lrck edge ( note 35 ) tmblr ? 40 - 40 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? ( note 35 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 35 ) tblr 50 - - ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 33. msbs, bckp bits = ?00? or ?11?. note 34. msbs, bckp bits = ?01? or ?10?. note 35. bick rising edge must not occur at the same time as lrck edge.
[ak4373] ms0991-e-00 2008/09 - 21 - parameter symbol min typ max units control interface timing (3-wire serial mode) cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn edge to cclk ? ? ( note 37 ) tcss 50 - - ns cclk ? ? to csn edge ( note 37 ) tcsh 50 - - ns control interface timing (i 2 c bus mode): ( note 36 ) scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 38 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s capacitive load on bus cb - - 400 pf setup time for stop condition tsu:sto 0.6 - - s pulse width of spike noise suppressed by input filter tsp 0 - 50 ns power-down & reset timing pdn pulse width ( note 39 ) tpd 150 - - ns note 36. i 2 c is a registered trademark of philips semiconductors. note 37. cclk rising edge must not occur at the same time as csn edge. note 38. data must be held long enough to bridge the 300ns-transition time of scl. note 39. the ak4373 can be reset by the pdn pin = ?l?. timing diagram mcki input measurement point vss3 tacw t acw vss3 1/fclk 1000pf 100k vac figure 8. mcki ac coupling timing
[ak4373] ms0991-e-00 2008/09 - 22 - lrck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%dvdd 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 dmck = tmckl x fmck x 100 figure 9. clock timing (pll/ext master mode) lrck bick 50%dvdd dbck tdbf 50%dvdd tlrckh tbck bick 50%dvdd (bckp = "0") (bckp = "1") tsds sdti vil tsdh vih figure 10. audio interface timing (pll/ext master mode, dsp mode, msbs = ?0?)
[ak4373] ms0991-e-00 2008/09 - 23 - lrck bick 50%dvdd dbck tdbf 50%dvdd tlrckh tbck bick 50%dvdd (bckp = "1") (bckp = "0") tsds sdti vil tsdh vih figure 11. audio interface timing (pll/ext master mode, dsp mode, msbs = ?1?) lrck 50%dvdd bick 50%dvdd tsds sdti vil tsdh vih tblr tbckl figure 12. audio interface timing (pll/ ext master mode, except dsp mode)
[ak4373] ms0991-e-00 2008/09 - 24 - 1/fs lrck vih tlrckh vil tbck bick tbckh tbckl vih vil tblr bick vih vil (bckp = "0") (bckp = "1") figure 13. clock timing (pll slave mode; pll reference clock = lrck or bick pin, dsp mode, msbs = ?0?) 1/fs lrck vih tlrckh vil tbck bick tbckh tbckl vih vil tblr bick vih vil (bckp = "1") (bckp = "0") figure 14. clock timing (pll slave mode; pll reference clock = lrck or bick pin, dsp mode, msbs = ?1?)
[ak4373] ms0991-e-00 2008/09 - 25 - 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%dvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 figure 15. clock timing (pll slave mode; pll reference clock = mcki pin, except dsp mode) lrck bick tsds sdti vil tsdh vih tlrb tlrckh msb vil vih vil vih bick vil vih (bckp = "0") (bckp = "1") figure 16. audio interface timing (pll slave mode, dsp mode; msbs = ?0?)
[ak4373] ms0991-e-00 2008/09 - 26 - lrck bick tsds sdti vil tsdh vih tlrb tlrckh msb vil vih vil vih bick vil vih (bckp = "1") (bckp = "0") figure 17. audio interface timing (pll slave mode, dsp mode, msbs = ?1?) 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 18. clock timing (ext slave mode)
[ak4373] ms0991-e-00 2008/09 - 27 - lrck vih vil tblr bick vih vil tlrb tsds sdti vil tsdh vih figure 19. audio interface timing (pll/ ext slave mode, except dsp mode) csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil a6 a5 r/w tcck tcsh figure 20. write command input timing csn vih vil tcsh cclk vih vil cdtio vih tcsw vil d1 d0 d2 tcss figure 21. write data input timing
[ak4373] ms0991-e-00 2008/09 - 28 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 22. i 2 c bus mode timing tpd pdn vil figure 23. power down & reset timing
[ak4373] ms0991-e-00 2008/09 - 29 - operation overview system clock there are the following five clock modes to interface with external devices ( table 2 and table 3 ). mode pmpll bit m/s bit pll3-0 bits figure pll master mode ( note 40 ) 1 1 see table 5 figure 24 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 5 figure 25 pll slave mode 2 (pll reference clock: lrck or bick pin) 1 0 see table 5 figure 26 figure 27 ext slave mode 0 0 x figure 28 ext master mode 0 1 x figure 29 note 40. if m/s bit = ?1?, pmpll bit = ?0? and mcko bit = ?1? during the setting of pll master mode, the invalid clocks are output from mcko pin when mcko bit is ?1?. table 2. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin lrck pin 0 l pll master mode 1 selected by ps1-0 bits selected by pll3-0 bits output (selected by bcko bit) output (1fs) 0 l pll slave mode (pll reference clock: mcki pin) 1 selected by ps1-0 bits selected by pll3-0 bits input ( 32fs) input (1fs) pll slave mode (pll reference clock: lrck or bick pin) 0 l gnd input (selected by pll3-0 bits) input (1fs) ext slave mode 0 l selected by fs1-0 bits input ( 32fs) input (1fs) ext master mode 0 l selected by fs1-0 bits output (selected by bcko bit) output (1fs) table 3. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak4373 is power-down mode (pdn pin = ?l?) and exits reset st ate, the ak4373 is slave mode. after exiting reset state, the ak4373 goes to master mode by changing m/s bit = ?1?. when the ak4373 is in master mode, lrck and bick pins are a floating state until m/s bit becomes ?1?. lrck and bick pins of the ak4373 should be pulled-down or pulled-up by a resistor (about 100k ) externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 4. select master/slave mode
[ak4373] ms0991-e-00 2008/09 - 30 - pll mode (pmpll bit = ?1?) when pmpll bit is ?1?, a fully integrated analog phase lock ed loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 5 , whenever the ak4373 is supplied to a stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or sampling frequency changes. 1) setting of pll mode r and c of vcoc pin mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ] c[f] pll lock time (max) 0 0 0 0 0 lrck pin 1fs 6.8k 220n 160ms (default) 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 10k 10n 4ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 10k 10n 4ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 40ms 5 0 1 0 1 mcki pin 12.288mhz 10k 4.7n 40ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 40ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 40ms 9 1 0 0 1 mcki pin 25mhz 15k 330n 200ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms others others n/a table 5. setting of pll mode (*fs: sampling frequency) (n/a: not available) 2) setting of sampling frequency in pll mode when pll reference clock input is the mcki pin, the samp ling frequency is selected by fs3-0 bits as defined in table 6 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz (default) 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a table 6. setting of sampling frequency at pmpll bit = ?1? (reference clock = mcki pin) (n/a: not available) when pll2 bit is ?0? (pll reference clock input is the lrck or bick pin), the sampling frequency is selected by fs3 and fs2 bits. ( table 7 ). mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 x x 7.35khz fs 12khz (default) 1 0 1 x x 12khz < fs 24khz 2 1 0 x x 24khz < fs 48khz others others n/a (x: don?t care, n/a: not available) table 7. setting of sampling frequency at pll2 bit = ?0? and pmpll bit = ?1? pll slave mode 2 (pll reference: clock: lrck or bick pin)
[ak4373] ms0991-e-00 2008/09 - 31 - pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, the lrck and bick pins go to ?l? and i rregular frequency clock is output from the mcko pin at mcko bit is ?1? before the pll goes to lock state after pmpll bit = ?0? ? ?1?. if mcko bit is ?0?, the mcko pin goes to ?l? ( table 8 ). after the pll is locked, a first period of lrck and bick may be invalid clock, but these clocks return to normal state after a period of 1/fs. when sampling frequency is changed, the bick and lrck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin lrck pin after that pmpll bit ?0? ? ?1? ?l? output invalid ?l? output ?l? output pll unlock (except above case) ?l? output invalid invalid invalid pll lock ?l? output see table 10 see table 11 1fs output table 8. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from the mcko pin before the pll goes to lock state after pmpll bit = ?0? ? ?1?. after that, the clock selected by table 10 is output from the mcko pin when pll is locked. dac output invalid data when the pll is unlocked. the output signal shoul d be muted by writing ?0? to dach and dacs bits. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid pll unlock ?l? output invalid pll lock ?l? output output table 9. clock operation at pll slave mode (pmpll bit = ?0?, m/s bit = ?0?)
[ak4373] ms0991-e-00 2008/09 - 32 - pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 12.288mhz, 13.5mhz, 24mhz, 25mhz or 27mhz) is input to the mcki pin, the mcko, bick and lrck clocks are generated by an internal pll circuit. the mcko output frequency is selected by ps1-0 bits ( table 10 ) and the output is enabled by mcko bit. the bick output frequency is selected between 32fs or 64fs, by bcko bit ( table 11 ). ak4373 dsp or p mcko bick lrck sdti bclk lrck sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz 13.5mhz, 24mhz, 25mhz, 27mhz mclk figure 24. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 10. mcko output frequency (pll mode, mcko bit = ?1?) bcko bit bick output frequency 0 32fs (default) 1 64fs table 11. bick output frequency at master mode
[ak4373] ms0991-e-00 2008/09 - 33 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to the mcki, bick or lrck pin. the required clock to the ak4373 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits ( table 5 ). a) pll reference clock: mcki pin bick and lrck inputs must be synchronized with mcko output. the phase between mcko and lrck is not important. the mcko pin outputs the frequency selected by ps1-0 bits ( table 10 ) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits ( table 6 ). ak4373 dsp or p mcko bick lrck sdti bclk lrck sdto mcki 1fs 32fs 11.2896mhz, 12mhz, 12.288mhz 13.5mhz, 24mhz, 25mhz, 27mhz mclk 256fs/128fs/64fs/32fs figure 25. pll slave mode 1 (pll reference clock: mcki pin)
[ak4373] ms0991-e-00 2008/09 - 34 - b) pll reference clock: bick or lrck pin sampling frequency corresponds to 7.35khz to 48khz by changing fs3-0 bits ( table 7 ). ak4373 dsp or p mcki bick lrck sdti bclk lrck sdto mcko 1fs 32fs or 64fs figure 26. pll slave mode 2 (pll reference clock: bick pin) ak4373 dsp or p mcki bick lrck sdti bclk lrck sdto mcko 1fs 32fs figure 27. pll slave mode 2 (pll reference clock: lrck pin) the external clocks (bick and lrck) mu st always be present whenever the dac is in operation (pmdac bit = ?1?). if these clocks are not provided, the ak4373 may draw excess cu rrent and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if the external clocks are not present, the dac must be in the power-down mode (pmdac bit = ?0?).
[ak4373] ms0991-e-00 2008/09 - 35 - ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the ak4373 changes to ext mode. master clock is input from the mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of a normal audio dac. the clocks required to operate are mcki (256fs, 512fs or 1024fs), lrck (fs) and bick ( 32fs). the master clock (mcki) should be synchronized with lrck. the phase between these clocks is not important. the input frequency of mcki is selected by fs1-0 bits ( table 12 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz 48khz (default) 1 x 0 1 1024fs 7.35khz 13khz 2 x 1 0 512fs 7.35khz 26khz 3 x 1 1 512fs 7.35khz 48khz table 12. mcki frequency at ext slave mode (p mpll bit = ?0?, m/s bit = ?0?) (x: don?t care) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher freque ncy of the master clock. the s/n of the dac output through hpl/hpr pins at fs=8khz is shown in table 13 . mode mcki s/n (fs=8khz, 20khzlpf + a-weighted) 0 256fs 2 512fs 56db 3 512fs 75db 1 1024fs 93db table 13. relationship between mcki and s/n of hpl/hpr pins the external clocks (mcki, bick and lrck) should always be present whenever the dac is in operation (pmdac bit = ?1?). if these clocks are not provided, the ak4373 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if the external clocks are not present, the dac must be in the power-down mode (pmdac bit = ?0?). ak4373 dsp or p mcki bick lrck sdti bclk lrck sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 28. ext slave mode
[ak4373] ms0991-e-00 2008/09 - 36 - ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the ak4373 becomes ext master mode by setting pmpll bit = ?0? and m/s bit = ?1?. master clock is input from the mcki pin, the internal pll circuit is not operated. the clock required to operate is mcki (256fs, 512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits ( table 14 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz 48khz (default) 1 x 0 1 1024fs 7.35khz 13khz 2 x 1 0 512fs 7.35khz 26khz 3 x 1 1 512fs 7.35khz 48khz table 14. mcki frequency at ext master mode (pmpll bit = ?0?, m/s b it = ?1?) (x: don?t care) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher freque ncy of the master clock. the s/n of the dac output through the hpl/hpr pins at fs=8khz is shown in table 15 . mode mcki s/n (fs=8khz, 20khzlpf + a-weighted) 0 256fs 2 512fs 56db 3 512fs 75db 1 1024fs 93db table 15. relationship between mcki and s/n of hpl/hpr pins mcki should always be present whenever the dac is in operation (pmdac bit = ?1?). if mcki is not provided, the ak4373 may draw excess current and it is not possible to ope rate properly because utilizes dynamic refreshed logic internally. if mcki is not present, the dac should be in the power-down mode (pmdac bit = ?0?). ak4373 dsp or p mcki bick lrck sdti bclk lrck sdto mcko 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs figure 29. ext master mode mcko output frequency mcko output frequency can be controlled by ps1/0 bits when mcko bit is ?1? regardless of any clock mode (pll/ext, master/slave). mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 16. mcko output frequency (ext mode, mcko bit = ?1?)
[ak4373] ms0991-e-00 2008/09 - 37 - system reset the pdn pin must be held to ?l? upon power-up. the 4373 s hould be reset by bringing pdn pin ?l? for 150ns or more. all of the internal register values are initialized by the sy stem reset. after exiting reset, vcom, dac, hpl, hpr, lout, rout, spp and spn switch to the power-down st ate. the contents of the control regi ster are maintained until the reset is completed. the dac exits reset and power down states by mcki after the pmdac bit is changed to ?1?. the dac is in power-down mode until mcki is input. audio interface format three types of data formats are available a nd are selected by setting the dif1-0 bits ( table 17 ). in all modes, the serial data is msb first, 2?s complement format. audio interface fo rmats can be used in both master and slave modes. lrck and bick are output from the ak4373 in master mode, but must be input to the ak4373 in slave mode. mode dif2 bit dif1 bit dif0 bit sdti (dac) bick figure 0 0 0 0 16 bit dsp mode 32fs table 18 1 0 0 1 16 bit lsb justified 32fs figure 34 2 0 1 0 16/20/24 bit msb justified 32fs or 48fs figure 36 (default) 3 0 1 1 16/20/24 bit i 2 s compatible 32fs or 48fs figure 37 4 1 0 0 20 bit lsb justified 40fs figure 35 5 1 0 1 24 bit lsb justified 48fs figure 35 6 1 1 0 20 bit dsp mode 40fs table 18 7 1 1 1 24 bit dsp mode 48fs table 18 table 17. audio interface format in modes 1- 5 the sdti is latched on the rising edge (? ?) of bick. in modes 0/6/7 (dsp mode), the audio i/f timing is changed by bckp and msbs bits ( table 18 , table 19 and table 20 ). dif2 dif1 dif0 msbs bckp a udio interface format figure 0 0 msb of sdti is latched by the falling edge (? ?) of the bick just after the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 30 (default) 0 1 msb of sdti is latched by the rising edge (? ?) of the bick just after the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 31 1 0 msb of sdti is latched by the 2nd falling edge (? ?) of the bick after the rising edge (? ?) of lrck. figure 32 0 0 0 1 1 msb of sdti is latched by the 2nd rising edge (? ?) of the bick after the rising edge (? ?) of lrck.. figure 33 table 18. audio interface format in mode 0
[ak4373] ms0991-e-00 2008/09 - 38 - dif2 dif1 dif0 msbs bckp a udio interface format figure 0 0 msb of sdti is latched by the falling edge (? ?) of the bick just after the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 38 (default) 0 1 msb of sdti is latched by the rising edge (? ?) of the bick just after the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 39 1 0 msb of sdti is latched by the 2nd falling edge (? ?) of the bick after the rising edge (? ?) of lrck. figure 40 1 1 0 1 1 msb of sdti is latched by the 2nd rising edge (? ?) of the bick after the rising edge (? ?) of lrck.. figure 41 table 19. audio interface format in mode 6 dif2 dif1 dif0 msbs bckp a udio interface format figure 0 0 msb of sdti is latched by the falling edge (? ?) of the bick just after the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 42 (default) 0 1 msb of sdti is latched by the rising edge (? ?) of the bick just after the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 43 1 0 msb of sdti is latched by the 2nd falling edge (? ?) of the bick after the rising edge (? ?) of lrck. figure 44 1 1 1 1 1 msb of sdti is latched by the 2nd rising edge (? ?) of the bick after the rising edge (? ?) of lrck.. figure 45 table 20. audio interface format in mode 7
[ak4373] ms0991-e-00 2008/09 - 39 - lrck bick ( 32fs ) 31 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 10 13 29 26 218 bick ( 64fs ) 63 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 16 48 15:msb, 0:lsb 1/fs 234 sdti(i) 0 15 5 8 7 1 4 3 2 6 0 15 5 8 7 1 4 3 2 6 0 14 14 lch rch sdti(i) 15 2 1 0 15 2 1 0 14 14 lch rch lrck (master) (slave) figure 30. mode 0 timing (bckp = ?0?, msbs = ?0?) bick ( 32fs ) 31 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 10 13 29 26 218 bick ( 64fs ) 63 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 16 48 15:msb, 0:lsb 1/fs 234 sdti(i) 0 15 5 8 7 1 4 3 2 6 0 15 5 8 7 1 4 3 2 6 0 14 14 lch rch sdti(i) 15 2 1 0 15 2 1 0 14 14 lch rch lrck lrck (master) (slave) figure 31. mode 0 timing (bckp = ?1?, msbs = ?0?) bick ( 32fs ) 31 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 10 13 29 26 218 bick ( 64fs ) 63 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 16 48 15:msb, 0:lsb 1/fs 234 sdti(i) 0 15 5 8 7 1 4 3 2 6 0 15 5 8 7 1 4 3 2 6 0 14 14 lch rch sdti(i) 15 2 1 0 15 2 1 0 14 14 lch rch lrck lrck (master) (slave) figure 32. mode 0 timing (bckp = ?0?, msbs = ?1?)
[ak4373] ms0991-e-00 2008/09 - 40 - bick ( 32fs ) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 10 13 29 26 218 bick ( 64fs ) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 16 48 15:msb, 0:lsb 1/fs 234 lch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 33. mode 0 timing (bckp = ?1?, msbs = ?1?) sdti bick lrck sdti 15 14 6 5 4 bick 3210 1514 ( 32fs ) 15 14 0 15 14 0 mode 1 don?t care don?t care 15:msb, 0:lsb mode 1 15 14 6 5 4 3 2 1 0 lch data rch data figure 34. mode 1 timing sdti lrck bick 19 0 19 0 mode 4 don?t care don?t care 19:msb, 0:lsb sdti mode 5 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 23 23 figure 35. mode 4, 5 timing
[ak4373] ms0991-e-00 2008/09 - 41 - lrck bick sdti 16bit don?t 0 14 15 14 15 lch rch care 14 0 15 sdti 20bit 18 19 18 19 4 1 0 don?t care 18 19 41 0 don?t care don?t care sdti 24bit 22 23 22 23 don?t care 22 23 don?t care 8 3 4 0 1 83 4 0 1 figure 36. mode 2 timing lrck lch rch bick don?t 0 14 15 15 care 14 0 15 19 18 19 4 1 0 don?t care 18 19 41 0 don?t care don?t care sdti 16bit sdti 20bit sdti 24bit 23 22 23 don?t care 22 23 don?t care 8 3 4 0 1 83 4 0 1 bick 6 14 15 15 14 6 15 sdti 16bit (32fs) 0 5 4 321 0 54 3 2 1 0 figure 37. mode 3 timing
[ak4373] ms0991-e-00 2008/09 - 42 - lrck bick ( 64fs ) 63 0 1 18 19 21 22 38 39 40 41 46 47 49 50 62 63 20 48 19:msb, 0:lsb 1/fs 242 sdti(i) 19 2 1 0 19 2 1 0 18 18 lch rch lrck (master) (slave) figure 38. mode 6 timing (bckp = ?0?, msbs = ?0?) lrck bick ( 64fs ) 63 0 1 18 19 21 22 38 39 40 41 46 47 49 50 62 63 20 48 19:msb, 0:lsb 1/fs 242 sdti(i) 19 2 1 0 19 2 1 0 18 18 lch rch lrck (master) (slave) figure 39. mode 6 timing (bckp = ?1?, msbs = ?0?) bick ( 64fs ) 63 0 1 18 19 21 22 38 39 40 41 46 47 49 50 62 63 20 48 19:msb, 0:lsb 1/fs 242 sdti(i) 19 2 1 0 19 2 1 0 18 18 lch rch lrck lrck (master) (slave) figure 40. mode 6 timing (bckp = ?0?, msbs = ?1?) bick ( 64fs ) 63 0 1 18 19 21 22 38 39 40 41 46 47 49 50 62 63 20 48 19:msb, 0:lsb 1/fs 242 sdti(i) 19 2 1 0 19 2 1 0 18 18 lch rch lrck lrck (master) (slave) figure 41. mode 6 timing (bckp = ?1?, msbs = ?1?)
[ak4373] ms0991-e-00 2008/09 - 43 - lrck bick ( 64fs ) 63 0 1 22 23 25 26 46 47 48 49 54 55 57 58 62 63 24 56 23:msb, 0:lsb 1/fs 250 sdti(i) 23 2 1 0 23 2 1 0 22 22 lch rch lrck (master) (slave) figure 42. mode 7 timing (bckp = ?0?, msbs = ?0?) lrck bick ( 64fs ) 63 0 1 22 23 25 26 46 47 48 49 54 55 57 58 62 63 24 56 23:msb, 0:lsb 1/fs 250 sdti(i) 23 2 1 0 23 2 1 0 22 22 lch rch lrck (master) (slave) figure 43. mode 7 timing (bckp = ?1?, msbs = ?0?) bick ( 64fs ) 63 0 1 22 23 25 26 46 47 48 49 54 55 57 58 62 63 24 56 23:msb, 0:lsb 1/fs 250 sdti(i) 23 2 1 0 23 2 1 0 22 22 lch rch lrck lrck (master) (slave) figure 44. mode 7 timing (bckp = ?1?, msbs = ?0?) bick ( 64fs ) 63 0 1 22 23 25 26 46 47 48 49 54 55 57 58 62 63 24 56 23:msb, 0:lsb 1/fs 250 sdti(i) 23 2 1 0 23 2 1 0 22 22 lch rch lrck lrck (master) (slave) figure 45. mode 7 timing (bckp = ?1?, msbs = ?1?)
[ak4373] ms0991-e-00 2008/09 - 44 - digital eq/hpf/lpf the ak4373 performs high/low pass filter, stereo separation em phasis, gain compensation, five programmable biquads, alc (automatic level control) and digital volume by digital domain for input data ( figure 46 ). hpf, lpf, fil3, and eq blocks are iir filters of 1 st order. the filter coefficient of hpf, lpf, fil3, and eq blocks can be set to any value. refer to the section of ?five programmable biquads?, ?a lc operation? and ?digital output volume? about five programmable biquads, alc and digital volume, respectively. fil3 coefficient also sets the attenua tion of the stereo separation emphasis. the combination of gn1-0 bit ( table 21 ) and eq coefficient set the compensation gain. fil3 block becomes hpf when f3as bits are ?0 ? and become lpf when f3as bits are ?1?. when eq, hpf and lpf bits are ?0?, eq, hpf and lpf blocks become ?through? (0db). when each filter coefficient is changed, each filter should be set to ?through?. hpf eq gain five biquads gn1-0 +24/+12/0db any coefficient f1a13-0 f1b13-0 any coefficient f2a13-0 f2b13-0 any coefficient eqa15-0 eqb13-0 eqc15-0 +12db 0db stereo separation emphasis gain compensation alc dvol lpf fil3 any coefficient f3a13-0 f3b13-0 f3as 0db -10db figure 46. digital eq/hpf/lpf (default) gn1 gn0 gain 0 0 0db (default) 0 1 +12db 1 x +24db table 21. gain select of gain block (x: don?t care)
[ak4373] ms0991-e-00 2008/09 - 45 - [filter coefficient setting] (1) high pass filter (hpf) fs: sampling frequency fc: cut-off frequency f: input signal frequency register setting ( note 41 ) hpf: f1a[13:0] bits =a, f1b[13:0] bits =b (msb=f1a13, f1b13; lsb=f1a0, f1b0) a = 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function amplitude phase h(z) = a 1 ? z ? 1 1 + bz ? 1 m(f) = a 2 ? 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (b+1)sin (2 f/fs) 1 - b + (b ? 1)cos (2 f/fs) (2) low pass filter (lpf) fs: sampling frequency fc: cut-off frequency f: input signal frequency register setting ( note 41 ) lpf: f2a[13:0] bits =a, f2b[13:0] bits =b (msb=f2a13, f2b13; lsb=f2a0, f2b0) a = 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function amplitude phase h(z) = a 1 + z ? 1 1 + bz ? 1 m(f) = a 2 + 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (b ? 1)sin (2 f/fs) 1 + b + (b+1)cos (2 f/fs)
[ak4373] ms0991-e-00 2008/09 - 46 - (3) stereo separation emphasis filter (fil3) 1) when fil3 is set to ?hpf? fs: sampling frequency fc: cut-off frequency k: filter gain [db] (0db k ? 10db) register setting ( note 41 ) fil3: f3as bit = ?0?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f3a13, f3b13; lsb=f3a0, f3b0) a = 10 k/20 x 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function amplitude phase h(z) = a 1 ? z ? 1 1 + bz ? 1 m(f) = a 2 ? 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (b+1)sin (2 f/fs) 1 - b + (b ? 1)cos (2 f/fs) 2) when fil3 is set to ?lpf? fs: sampling frequency fc: cut-off frequency k: filter gain [db] (0db k ? 10db) register setting ( note 41 ) fil3: f3as bit = ?1?, f3a [13:0] bits =a, f3b [13:0] bits =b (msb=f3a13, f3b13; lsb= f3a0, f3b0) a = 10 k/20 x 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function amplitude phase h(z) = a 1 + z ? 1 1 + bz ? 1 m(f) = a 2 + 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (b ? 1)sin (2 f/fs) 1 + b + (b+1)cos (2 f/fs)
[ak4373] ms0991-e-00 2008/09 - 47 - (4) eq fs: sampling frequency fc 1 : pole frequency fc 2 : zero-point frequency f: input signal frequency k: filter gain [db] (maximum +12db) register setting ( note 41 ) eqa[15:0] bits =a, eqb[13:0] bits =b, eqc[15:0] bits =c (msb=eqa15, eqb13, eqc15; lsb=eqa0, eqb0, eqc0) a = 10 k/20 x 1 + 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) b = 1 ? 1 / tan ( fc 1 /fs) 1 + 1 / tan ( fc 1 /fs) , c =10 k/20 x 1 ? 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) , transfer function amplitude phase h(z) = a + cz ? 1 1 + bz ? 1 m(f) = a 2 + c 2 + 2accos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (ab ? c)sin (2 f/fs) a + bc + (ab+c)cos (2 f/fs) note 41. [translation the filter coeffici ent calculated by the equations above fro m real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient setting register is sign bit.
[ak4373] ms0991-e-00 2008/09 - 48 - [filter coefficient setting example] 1) hpf block example: fs=44.1khz, fc=100hz f1a[13:0] bits = 01 1111 1100 0110 f1b[13:0] bits = 10 0000 0111 0100 2) lpf block example: fs=44.1khz, fc=10khz f2a[13:0] bits = 01 0001 0010 1100 f2b[13:0] bits = 00 0010 0101 0111 3) fil3 block example: fs=44.1khz, fc=4khz, gain=-6db, f3as bit = ?1? (lpf) f3a[13:0] bits = 00 0011 1010 0010 f3b[13:0] bits = 10 1110 1000 0000 4) eq block example: fs=44.1khz, fc 1 =300hz, fc 2 =3000hz, gain=+8db gain[db] +8db fc 1 fc 2 frequency eqa[15:0] bits = 0000 1001 0110 1110 eqb[13:0] bits = 10 0001 0101 1001 eqc[15:0] bits = 1111 1001 1110 1111
[ak4373] ms0991-e-00 2008/09 - 49 - five programmable biquads this block can be used as equalizer or notch filter. 5-band equalizer (eq1, eq2, eq3, eq4 and eq5) is on/off independently by eq1, eq2, eq3, eq4 and eq5 bits. when th e equalizer is off, the audio data passes this block by 0db gain. e1a15-0, e1b15-0 and e1c15-0 bits set the coefficient of eq1. e2a15-0, e2b15-0 and e2c15-0 bits set the coefficient of eq2. e3a15-0, e3b15-0 and e3c15-0 bits set the coefficient of eq3. e4a15-0, e4b15-0 and e4c15-0 bits set the coefficient of eq4. e5a15-0, e5b15-0 and e5c15-0 bits set the coefficient of eq5. the eqx (x=1 5) coefficient should be set when eqx bit = ?0? or pmdac bit = ?0?. fs: sampling frequency fo 1 ~ fo 5 : center frequency fb 1 ~ fb 5 : band width where the gain is 3db different from center frequency k 1 ~ k 5 : gain ( ? 1 k n 3) register setting ( note 42 ) eq1: e1a[15:0] bits =a 1 , e1b[15:0] bits =b 1 , e1c[15:0] bits =c 1 eq2: e2a[15:0] bits =a 2 , e2b[15:0] bits =b 2 , e2c[15:0] bits =c 2 eq3: e3a[15:0] bits =a 3 , e3b[15:0] bits =b 3 , e3c[15:0] bits =c 3 eq4: e4a[15:0] bits =a 4 , e4b[15:0] bits =b 4 , e4c[15:0] bits =c 4 eq5: e5a[15:0] bits =a 5 , e5b[15:0] bits =b 5 , e5c[15:0] bits =c 5 (msb=e1a15, e1b15, e1c15, e2a15, e2b15, e2c15, e3a15, e3b15, e3c15, e4a15, e4b15, e4c15, e5a15, e5b15, e5c15; lsb= e1a0, e1b0, e1c0, e2a0, e2b0, e2c0, e3a0, e3b0, e3c0, e4a0, e4b0, e4c0, e5a0, e5b0, e5c0) a n = k n x tan ( fb n /fs) 1 + tan ( fb n /fs) b n = cos(2 fo n /fs) x 2 1 + tan ( fb n /fs) , c n = 1 ? tan ( fb n /fs) 1 + tan ( fb n /fs) , (n = 1, 2, 3, 4, 5) transfer function h n (z) = a n 1 ? z ? 2 1 ? b n z ? 1 ? c n z ? 2 h(z) = 1 + h 1 (z) + h 2 (z) + h 3 (z) + h 4 (z) + h 5 (z) (n = 1, 2, 3, 4, 5) the center frequency should be set as below. fo n / fs < 0.497 note 42. [translation the filter coefficient calculated by th e equations above from real num ber to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient setting register is sign bit.
[ak4373] ms0991-e-00 2008/09 - 50 - alc operation the alc (automatic level control) is controlled by alc block when alc bit is ?1?. 1. alc limiter operation during alc limiter operation, when either lch or rch exceeds the alc limiter detection level ( table 22 ), the avl and avr values (same value) are attenuated automatically by the amount defined by the alc limiter att step ( table 23 ). when zelmn bit = ?0? (zero cross det ection is enabled), the avl and avr values are changed by alc limiter operation at the individual zero crossing points of lch and rch or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout period of both al c limiter and recovery operation ( table 24 ). when alc output level exceeds full-scale, ivl and ivr values are immedi ately (period: 1/fs) changed. when alc output level is less than full-scale, ivl and ivr values are changed at the individual zero crossi ng point of each channels or at the zero crossing timeout. when zelmn bit = ?1? (zero cross detection is disabled), avl and avr values are immediat ely (period: 1/fs) changed by alc limiter operation. attenuation step is fixed to 1 step regardless of the setting of lmat1-0 bits. the attenuate operation is done continuously until the i nput signal level becomes alc limiter detection level ( table 22 ) or less. after completing the attenuate operation, unless alc b it is changed to ?0?, the operation repeats when the input signal level exceeds lmth1-0 bits. lmth1 lmth0 alc limier detection level alc recovery waiting counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs (default) 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 22. alc limiter detection leve l / recovery counter reset level alc1 limiter att step (0.375db/step) lmat1 lmat0 alc1 output lmth 0 0 1 (default) 0 1 2 1 0 2 1 1 1 table 23. alc limiter att step zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 24. alc zero crossing timeout period
[ak4373] ms0991-e-00 2008/09 - 51 - 2. alc recovery operation alc recovery operation wait for the wtm2-0 bits ( table 25 ) to be set after completing alc limiter operation. if the input signal does not exceed ?alc rec overy waiting counter reset level? ( table 22 ) during the wait time, alc recovery operation is completed. the avl and avr values are automatically incremented by rgain1-0 bits ( table 26 ) up to the set reference level ( table 27 ) with zero crossing detection which timeout period is set by ztm1-0 bits ( table 24 ). then the avl and avr are set to the same value for both channe ls. alc recovery operation is executed at a period set by wtm2-0 bits. when zero cross is detected at both channels during the wait period set by wtm2-0 bits, alc recovery operation waits until wtm2-0 period and th e next recovery operation is complete d. if ztm1-0 is longer than wtm2-0 and no zero crossing occurs, alc recovery operati on is made at a period set by ztm1-0 bits. for example, when the current avol value is 30h and rgain1 -0 bits are set to ?01?, avol is changed to 32h by the auto limiter operation and then the input signal level is ga ined by 0.75db (=0.375db x 2). when the avol value exceeds the reference level (ref7-0), th e avol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. alc operation corresponds to the impulse noise. when the impulse noise is input, alc recovery operation is faster than a normal recovery operation (fast recovery operation). when large noise is i nput to microphone instantaneously, quality of small signal level in the large noise can be improved by this fast recovery operation. the speed of fast recovery operation is set by rfst1-0 bits ( table 28 ). alc recovery operation waiting period wtm2 wtm1 wtm0 8khz 16khz 44.1khz 0 0 0 128/fs 16ms 8ms 2.9ms (default) 0 0 1 256/fs 32ms 16ms 5.8ms 0 1 0 512/fs 64ms 32ms 11.6ms 0 1 1 1024/fs 128ms 64ms 23.2ms 1 0 0 2048/fs 256ms 128ms 46.4ms 1 0 1 4096/fs 512ms 256ms 92.9ms 1 1 0 8192/fs 1024ms 512ms 185.8ms 1 1 1 16384/fs 2048ms 1024ms 371.5ms table 25. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 26. alc recovery gain step
[ak4373] ms0991-e-00 2008/09 - 52 - ref7-0 gain(db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54.0 0.375db 00h mute table 27. reference level at alc recovery operation rfst1 bit rfst0 bit recovery speed 0 0 4 times (default) 0 1 8 times 1 0 16times 1 1 n/a table 28. fast recovery speed setting (n/a: not available)
[ak4373] ms0991-e-00 2008/09 - 53 - 3. example of alc operation table 29 shows the examples of the alc setting. fs=8khz fs=44.1khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 23.2ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same or longer data as ztm1-0 bits. 001 32ms 011 23.2ms ref7-0 maximum gain at recovery operation e1h +30db e1h +30db avl7-0, avr7-0 gain of avol e1h +30db e1h +30db lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 00 4 times 00 4 times alc alc enable 1 enable 1 enable table 29. example of the alc setting the following registers should not be changed during alc ope ration. these bits should be changed after alc operation is finished by alc bit = ?0? or pmdac bit = ?0?. ? lmth1-0, lmat1-0, wtm2-0, ztm1-0, rgain1-0, ref7-0, zelmn, rfst1-0 manual mode * the value of avol should be the same or smaller than ref?s wr (ztm1-0, wtm2-0, rfst1-0) wr (ref7-0) wr (avl/r7-0) wr (lmat1-0, rgain0, zelmn, lmth0; alc= ?1?) example: limiter = zero crossing enable recovery cycle = 32ms@8khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? (1) addr=06h, data=14h (2) addr=08h, data=e1h (5) addr=07h, data=01h (3) addr=09h&0ch, data=e1h alc operation wr (rgain1, lmth1) (4) addr=0bh, data=00h note : wr : write figure 47. registers set-up sequence at alc operation
[ak4373] ms0991-e-00 2008/09 - 54 - digital volume at alc block (manual mode) the digital volume at alc block changes to a manual mode when alc bit is ?0?. this mode is used in the case shown below. 1. after exiting reset state, set-up the registers for alc operation (ztm1-0, lmth1-0 and etc) 2. when the registers for alc operation (limiter pe riod, recovery period and etc) are changed. for example; when the change of the sampling frequency. avl7-0 and avr7-0 bits set the gain of the volume control at alc block ( table 30 ). the avol value is changed at zero crossing or timeout. zero crossing timeout period is set by ztm1-0 bits. when alc is not used, avl7-0 and avr7-0 bits should be set to ?91h? (0db). avl7-0 avr7-0 gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 30. alc block digital volume setting
[ak4373] ms0991-e-00 2008/09 - 55 - when writing to the avl7-0 and avr7-0 bits continuously, the control register s hould be written by an interval more than zero crossing timeout. if not, avl and avr are not changed since zero crossing counter is reset at every write operation. if the same register value as the previous write operation is written to avl and avr, this write operation is ignored and zero crossing counter is not reset. therefore, avl and avr can be written by an interval less than zero crossing timeout. a lc bit a lc status disable enable disable a vl7-0 bits e1h(+30db) a vr7-0 bits c6h(+20db) internal avl e1h(+30db) e1(+30db) --> f1(+36db) e1(+30db) internal avr c6h(+20db) e1(+30db) --> f1(+36db) c6h(+20db) (1) (2) figure 48. avol value during alc operation (1) the avl value becomes the start value if the avl and avr are different wh en the alc starts. the wait time from alc bit = ?1? to alc operation start by avl7-0 bits is at most recovery time (wtm2-0 bits) plus zerocross timeout period (ztm1-0 bits). (2) writing to avl and avr registers (09h and 0ch) is i gnored during alc operation. after alc is disabled, the avol changes to the last written data by zero crossing or timeout. when alc is enabled again, alc bit should be set to ?1? by an interval more than zero crossing timeout period after alc bit = ?0?.
[ak4373] ms0991-e-00 2008/09 - 56 - de-emphasis filter the ak4373 includes the digital de-emphasis filter (tc = 50/15 s) by iir filter. setting the dem1-0 bits enables the de-emphasis filter ( table 31 ). dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 31. de-emphasis control digital output volume the ak4373 has a digital output volume (256 levels, 0.5db step, mute). the volume can be set by the dvl7-0 and dvr7-0 bits. the volume is included in front of a dac block. the input data of dac is changed from +12 to ?115db or mute. when the dvolc bit = ?1?, the dvl7-0 bits contro l both lch and rch attenuation levels. when the dvolc bit = ?0?, the dvl7-0 bits control lch level and dvr7-0 bits cont rol rch level. this volume has a soft transition function. the dvtm bit sets the transition time between set values of dvl/r7-0 bits as either 1061/fs or 256/fs ( table 33 ). when dvtm bit = ?0?, a soft transition between the set values occurs (1062 levels). it takes 1061/fs (=24ms@fs=44.1khz) from 00h (+12db) to ffh (mute). dvl/r7-0 gain 00h +12.0db 01h +11.5db 02h +11.0db : : 18h 0db (default) : : fdh ? 114.5db feh ? 115.0db ffh mute ( ? ) table 32. digital volume code table transition time between dvl/r7-0 bits = 00h and ffh dvtm bit setting fs=8khz fs=44.1khz 0 1061/fs 133ms 24ms (default) 1 256/fs 32ms 6ms table 33. transition time setting of digital output volume
[ak4373] ms0991-e-00 2008/09 - 57 - soft mute soft mute operation is performed in the digital domain. when the smute bit changed to ?1?, the output signal is attenuated by ? (?0?) during the cycle set by the dvtm bit. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the va lue set by the dvl/r7-0 bits during the cycle set of the dvtm bit. if the soft mute is cancelled within the cycle set by the dvtm bit after starting the operation, the attenuation is discontinued and returned to the value set by the dvl/r7-0 bits. the soft mute is effective for changing the signal source without stopping the signal transmission ( figure 49 ). smute bit a ttenuation dvtm bit dvl/r7-0 bits - dvtm bit gd gd (1) (2) (3) a nalog output figure 49. soft mute function (1) the output signal is attenuated until ? (?0?) by the cycle set by the dvtm bit. (2) analog output corresponding to digital input has group delay (gd). (3) if the soft mute is cancelled within the cycle set by the dvtm bit, the attenuation is discounted and returned to the value set by the dvl/r7-0 bits.
[ak4373] ms0991-e-00 2008/09 - 58 - analog mixing: monaural input when pmmin bit is set to ?1?, the mono input is powered-up. when minh/s bits are set to ?1?, the input signal from the min+/min- pin is output to hp-amp/speaker-amp. the external resisters ri adjust the signal gain of min+/min- input. if the analog mixing block will use as a single-ended, the min- pin should be connected to vss1 in series with capacitor to avoid induced external noise.( figure 51 ) when the headphone output type is differential (hpbtl b it = ?1?), hvdd should be the same as the voltage of avdd to use the path from min to hp-amp(minh bit = ?1?). min - pin rin ? + min+ pin ? + 20k(typ) minh/s bit hp amp / spk amp 20k(typ) dac dach/s bit ? + 20k(typ) rin ? + figure 50. block diagram of monaural input (differential input) min- pin rin ? + min+ pi n ? + 20k(typ) minh/s bit hp amp / spk amp 20k(typ) dac dach/s bit ? + 20k(typ) ? + figure 51. block diagram of monaural input (single input)
[ak4373] ms0991-e-00 2008/09 - 59 - analog output control hpbtl and pseudo bits select the output type, si ngle-ended, differential or pseudo cap-less ( table 34 ). available pins and bits are changed at each output type. hpbtl bit pseudo bit headphone output type figure table 0 0 single-ended (default) figure 1 table 35 1 0 differential figure 2 table 36 0 1 pseudo cap-less figure 3 table 37 1 1 n/a table 34. headphone output type select (n/a: not available) pin / control available pin / bit pin hpl/r, lout/rout spp/spn power management pmhpl/r pmspk(sppsn) switch control from min to hp-amp minh mins switch control from dac to hp-amp dach dacs gain control hpg spkg[1:0] table 35. available pin / bit (single- ended, hpbtl bit = pseudo bit = ?0?) pin / control available pin / bit pin hpl+/- hpr +/- power management pmhpl pmhpr switch control from min to hp-amp minh minh switch control from dac to hp-amp dach dach gain control hpg hpg table 36. available pin / bit (differen tial, hpbtl bit = ?1?, pseudo bit = ?0?) pin / control available pin / bit pin hpl/r hvcm power management pmhpl/r pmhpl or pmhpr switch control from min to hp-amp minh - switch control from dac to hp-amp dach - gain control hpg - table 37. available pin / bit (pseudo cap-less, hpbtl bit = ?0?, pseudo bit = ?1?)
[ak4373] ms0991-e-00 2008/09 - 60 - stereo line output (lout/rout pins) the common voltage is 0.5 x hvdd when vbat bit = ?0? ( table 40 ). the load resistance is 10k ? (min). stereo line out amplifier is shared with h eadphone amplifier (hpbtl bit = pseudo bit = ?0? in table 38 ). when pmhpl/r and hpmtn bits are ?1?, th e stereo line output is powered-up ( figure 52 ). stereo line out amplifier is prohibited from using headphone output at the same time. headphone output the power supply voltage for the headphone-amp is supplied from the hvdd pin and the output level is centered on the hvdd/2 when vbat bit = ?0?. if hvdd voltage becomes lowe r, the output signal might be distorted while the amplitude is maintained. the load resistance is 16 (min). hpbtl and pseudo bits sel ect the output type, single-ended or differential or pseudo cap-less. when the hp btl bit is ?1?, hpl/hpr/spp/spn pins become hpl+/hpl-/hpr+/hpr- pins, respectively. when the pseudo b it is ?1?, the spn pin beco me the hvcm pin. hpg bit selects the output voltage ( table 38 ). hpbtl pseudo hpg output type out put pins output voltage [vpp] 0 0 0 single-ended hpl, hpr 0.6 x avdd 0 0 1 single-ended hpl, hpr 0.91 x avdd 1 0 0 differential hpl+/-, hpr+/- 1.2 x avdd 1 0 1 differential hpl+/-, hpr+/- 1.82 x avdd 0 1 0 pseudo cap-less hpl, hpr, hvcm 0.6 x avdd 0 1 1 pseudo cap-less hpl, hpr, hvcm 0.91 x avdd 1 1 x n/a table 38. headphone-amp output type and output voltage (x: don?t care, n/a: not available) when the hpmtn bit is ?0?, the common voltage of h eadphone-amp falls and the outputs (hpl/r and hpl+/- and hpr+/- and hvcm pins) go to ?l? (vss2). when the hpmt n bit is ?1?, the common voltage rises to hvdd/2 at vbat bit = ?0?. a capacitor between the mutet pin and ground reduces pop noise at power-up. rise/fall time constant is in proportional to hvdd voltage and the capacitor at mutet pin. [example]: a capacitor between the mutet pin and ground = 1.0 f30%, hvdd=3.6v: rising time (0.8 x hvdd/2): 150ms(typ), 260ms(max) at hpmtn bit = ?0? ? ?1? time until the common voltage goes to vss2: 140ms(typ), 260ms(max) at hpmtn bit = ?1? ? ?0? when pmhpl and pmhpr bits are ?0?, the headphone-amp is powered-down, and the outputs (hpl and hpr pins) go to ?l? (vss2). pmhpl bit, pmhpr bit (1) (2) (4) (3) hpmtn bit hpl/r pins hpl+/- pins hpr+/- pins hvcm pin figure 52. power-up/power-down timing for headphone-amp (1) headphone-amp power-up (pmhpl, pmhpr b it = ?1?). the outputs are still vss2. (2) headphone-amp common voltage rises up (hpmtn bit = ?1?). common voltage of headphone-amp is rising. (3) headphone-amp common voltage falls down (hpmtn bit = ?0?). common voltage of headphone-amp is falling. (4) headphone-amp power-down (pmhpl, pmhpr bit = ?0?). the outputs are vss2. if the power supply is switched off or headphone-amp is powered-down before the co mmon voltage changes to vss2, pop noise occurs.
[ak4373] ms0991-e-00 2008/09 - 61 - 1) single-ended output (hpbtl bit = ?0?, pseudo bit = ?0?) the cut-off frequency (fc) of headphone-amp depends on an external resistor and a capacitor. table 39 shows the cut off frequency and the output power for various resistor /capacitor combinations. the headphone impedance r l is 16 . output powers are shown at hvdd = 2.7, 3.3 and 3.8v. the output voltage of headphone is 0.6 x avdd (vpp). ak4373 hp-amp 16 headphone c r figure 53. external circuit example of headphone (single-ended output) output power [mw]@0dbfs( note 43 ) hpg bit r [ ] c [ f] fc [hz] hvdd=2.7v avdd=2.7v hvdd=3.3v avdd=3.3v hvdd=3.8v avdd=3.3v 220 45 0 100 100 20 30 30 100 70 6.8 47 149 10 15 15 100 50 0 16 47 106 5.0 7.5 7.5 220 45 0 100 100 44 ( note 44 ) 67 ( note 44 ) 70 22 62 1 100 10 137 0.9 1.3 1.3 table 39. external circuit example (single-ended output) note 43. output power at 16 load. note 44. output signal is clipped.
[ak4373] ms0991-e-00 2008/09 - 62 - 2) differential output (hpbtl b it = ?1? pseudo bit = ?0?) for differential output, no external ac coupling capacitor is required. power management (power up/down control) of l/rch is controlled by setting pmhpl/pmhpr bits respectively. the common voltage control of headphone-amp is controlled by setting htmtn bit. the common voltage is shown in table 40 . hpbtl bit should be changed when both speaker and headphone amps are powered-down. ak4373 hpl+ pin hpl ? pin hpr+ pin hpr ? pin + ? + ? headphone lch headphone rch figure 54. external circuit example of headphone (differential output)
[ak4373] ms0991-e-00 2008/09 - 63 - 3) pseudo cap-less output (hpbtl bit = ?0?, pseudo bit =?1?) in case of pseudo cap less, no external ac coupling capacitor is required as well as btl mode. this pseudo cap less mode is also available for normal 3-pin headphone mini jack while btl mode requires a closed system with 4-wire connection. power management (power up/down control) of vcom amp for hp-amp is controlled by setting pmhpl bit or pmhpr bit. the common voltage control of headphone-amp and vcom-amp is controlled by setting htmtn bit. the common voltage is shown in table 40 . pseudo bit should be changed when both speaker and headphone amps are powered-down. in this mode, hpbtl and dacs and mins bits must be ?0?. hpl pin hp-amp 16 r hvcm pin vcom amp for hp-amp headphone hpr pin hp-amp r 16 figure 55. external circuit example of headphone (pseudo cap-less output) when hvdd is directly supplied from the battery in the mobile phone system, rf noise may influences headphone output performance. when vbat bit is set to ?1?, hp-amp psrr for the noise applied to hvdd is improved. in this case, hp-amp common voltage is 0.64 x avdd (typ). when avdd is 3.3v, common voltage is 2.1v. therefore, when hvdd voltage becomes lower than 4.2v, th e output signal will be clipped easily. vbat bit 0 1 common voltage [v] 0.5 x hvdd 0.64 x avdd table 40. hp-amp common voltage
[ak4373] ms0991-e-00 2008/09 - 64 - speaker output (spp/spn pins) recommended power supply range is 2.6v to 4.0v. if hvdd volta ge becomes low, the output signal might be distorted while the amplitude is maintain ed. speaker-amp is available at hpbtl bit = pseudo bit = ?0?. speaker type dynamic speaker piezo (ceramic) speaker load resistance (min) 8 50 load capacitance (max) 30pf 3 f note 21. load impedance is total impedance of series re sistance (rseries) and piezo sp eaker impedance at 1khz in 34hfigure 56. load capacitance is capacitance of piezo speaker. wh en piezo speaker is used, 20 or more series resistors should be conn ected at both spp and spn pins, respectively. table 41. speaker type and power supply range the dac signal is input to the speaker-amp as [(l+r)/2]. the speaker-amp is mono and btl output. the gain is set by spkg1-0 bits. output level depends on avdd voltage and spkg1-0 bits. gain spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 +4.43db +6.43db (default) 01 +6.43db +8.43db 10 +10.65db +12.65db 11 +12.65db +14.65db table 42. spk-amp gain spk-amp output (dac input = 0dbfs) avdd hvdd spkg1-0 bits alc bit = ?0? alc bit = ?1? (lmth1-0 bits = ?00?) 00 3.30vpp 3.11vpp 01 4.15vpp ( note 45 ) 3.92vpp 10 6.75vpp ( note 45 ) 6.37vpp ( note 45 ) 3.3v 11 8.50vpp ( note 45 ) 8.02vpp ( note 45 ) 00 3.30vpp 3.11vpp 01 4.15vpp 3.92vpp 10 6.75vpp ( note 45 ) 6.37vpp ( note 45 ) 3.3v 4.0v 11 8.50vpp ( note 45 ) 8.02vpp ( note 45 ) note 45. the output level is calculated by assuming that output signal is not clipped. in actual case, output signal may be clipped when dac outputs 0db fs signal. dac output level should be set to lower level by setting digital volume so that speaker-amp output level is 4.0v pp (hvdd=3.3v) or 4.8vpp ( hvdd=4v) or less and output signal is not clipped. table 43. spk-amp output level
[ak4373] ms0991-e-00 2008/09 - 65 - fs=44.1khz register name comment data operation lmth1-0 limiter detection level 00 ? 2.5dbfs zelmn limiter zero crossi ng detection 0 enable ztm1-0 zero crossing timeout period 10 11.6ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same or longer data as ztm1-0 bits 011 23.2ms ref7-0 maximum gain at recovery operation c1h +18db avl7-0, avr7-0 gain of avol 91h 0db lmat1-0 limiter att step 00 1 step rgain1-0 recovery gain step 00 1 step alc alc enable 1 enable table 44. alc operation exam ple of speaker playback when a piezo speaker is used, two resistances more than 20 should be connected between spp/spn pins and speaker in series, respectively, as shown in figure 56 . zener diodes should be inserted between speaker and gnd as shown in figure 56 , in order to protect spk-amp of the ak4373 from the pow er that the piezo speaker outputs when the speaker is pressured. zener diodes of the following zener voltage should be used. 0.92 x hvdd zener voltage of zener diodo (zd in figure 56 ) hvdd+0.3v ex) in case of hvdd = 3.8v: 3.5v zd 4.1v for example, zener diode which zener voltage is 3.9v (min: 3.7v, max: 4.1v) can be used. spp spk-amp spn figure 56. speaker output circuit (load capacitance > 30pf)
[ak4373] ms0991-e-00 2008/09 - 66 - speaker-amp is powered-up/down by pmspk bit. when pmspk bit is ?0?, both spp and spn pin are in hi-z state. when pmspk bit is ?1? and sppsn bit is ?0?, the speaker-amp enters power-sav e mode. in this mode, the spp pin is placed in hi-z state and the spn pi n changes to hvdd/2 voltage. power-save mode can reduce pop noise at power-up and power-down. pmspk sppsn mode spp spn 0 x power-down vss2 vss2 (default) 0 power-save hi-z hvdd/2 1 1 normal operation normal operation normal operation table 45. speaker-amp mode setting (x: don?t care) pmspk bit sppsn bit spp pin spn pin hvdd/2 hvdd/2 hi-z hi-z >1ms >0 vss2 vss2 vss2 vss2 figure 57. power-up/power-down timing for speaker-amp
[ak4373] ms0991-e-00 2008/09 - 67 - serial control interface (1) 3-wire serial control mode (i2c pin = ?l?) write only internal registers may be written by usi ng the 3-wire p interface pins (csn, ccl k and cdti). the data on this interface consists of read/write (fixed to ?1?), re gister address (msb first, 7bits) and control data (msb first, 8bits). each bit is clocked in on the rising edge (? ?) of cclk. address and data are latched on the 16th cclk rising edge (? ?) after csn falling edge(? ?). clock speed of cclk is 5mhz (max). the value of internal registers are initialized by pdn pin = ?l?. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti a6 a5 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a6-a0: register address d7-d0: control data ?1? clock, ?h? or ?l? clock, ?h? or ?l? ?h? or ?l? ?h? or ?l? figure 58. serial control i/f timing
[ak4373] ms0991-e-00 2008/09 - 68 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4373 supports the fast-mode i 2 c-bus (max: 400khz). pull-up resistors at sda and scl pins should be connected to (dvdd+0.3)v or less voltage. (2)-1. write operations figure 59 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 65 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant six bits of the slave address are fixed as ?001001?. the next bit is cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) sets these device address bits ( figure 60 ). if the slave address matches that of the ak4373, the ak4373 generates an acknowledge and the operation is executed. the master must generate the acknowledge-relate d clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 66 ). r/w bit value of ?1? indicates that th e read operation is to be executed. ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4373. the format is msb first, and those most significant bit is fixed to zeros ( figure 61 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 62 ). the ak4373 generates an acknowledge after each byte is received. a data transfer is always terminated by stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 65 ). the ak4373 can perform more than one by te write operation per sequence. after receipt of the third byte the ak4373 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 6-bit address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 4fh prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only change when the clock signal on the scl line is low ( figure 67 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 59. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 1 cad0 r/w (cad0 must match with the cad0 pin) figure 60. the first byte 0 a6 a5 a4 a3 a2 a1 a0 figure 61. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 62. byte structure after the second byte
[ak4373] ms0991-e-00 2008/09 - 69 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the ak4373. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the inte rnal 6-bit address counter is increm ented by one, and the next data is automatically taken into the next address. if the addre ss exceeds 4fh prior to generating stop condition, the address counter will ?roll over? to 00h and the data of 00h will be read out. the ak4373 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the ak4373 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address ?n ?, the next current read operation would access data from the address ?n+1?. afte r receipt of the slave address with r/w bit ?1?, the ak4373 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknow ledge but generates stop condition instead, the ak4373 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 63. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. th e master issues start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave addr ess with the r/w bit ?1?. the ak4373 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge but generates stop condition instead, the ak4373 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 64. random address read
[ak4373] ms0991-e-00 2008/09 - 70 - scl sda stop condition start condition s p figure 65. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 66. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 67. bit transfer on the i 2 c-bus
[ak4373] ms0991-e-00 2008/09 - 71 - register map add r register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmmin pmspk 0 pmdac 0 0 01h power management 2 0 hpmtn p mhpl pmhpr m/s mckac mcko pmpll 02h signal select 1 sppsn mins dacs 0 hpbtl 0 pseudo 0 03h signal select 2 0 0 0 spkg1 spkg0 0 0 0 04h mode control 1 pll3 pll2 pll1 pll0 bcko dif2 dif1 dif0 05h mode control 2 ps1 ps0 fs3 msbs bckp fs2 fs1 fs0 06h timer select dvtm wtm2 ztm1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control avl 7 avl6 avl5 avl4 avl 3 avl2 avl1 avl0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0bh alc mode control 3 rgain1 lmth1 0 0 0 frn vbat 0 0ch rch input volume control avr7 avr6 avr5 avr4 avr3 avr2 avr1 avr0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 0eh mode control 3 0 0 smute dvolc 0 0 dem1 dem0 0fh mode control 4 0 0 0 0 avolc hpm minh dach 10h power management 3 0 0 hpg 0 0 0 0 0 11h digital filter select 1 gn1 gn0 lpf hpf eq fil3 0 pfsel 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h reserved 0 0 0 0 0 0 0 0 21h reserved 0 0 0 0 0 0 0 0 22h reserved 0 0 0 0 0 0 0 0 23h reserved 0 0 0 0 0 0 0 0 24h reserved 0 0 0 0 0 0 0 0 25h reserved 0 0 0 0 0 0 0 0 26h reserved 0 0 0 0 0 0 0 0 27h reserved 0 0 0 0 0 0 0 0 28h reserved 0 0 0 0 0 0 0 0 29h reserved 0 0 0 0 0 0 0 0 2ah reserved 0 0 0 0 0 0 0 0 2bh reserved 0 0 0 0 0 0 0 0 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8
[ak4373] ms0991-e-00 2008/09 - 72 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 31h reserved 0 0 0 0 0 0 0 0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1 a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2 a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3 a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4 a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 note 46. pdn pin = ?l? resets the registers to their default values. note 47. unused bits indicated ?0? must contain a ?0? value.
[ak4373] ms0991-e-00 2008/09 - 73 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmmin pmspk 0 pmdac 0 0 default 0 0 0 0 0 0 0 0 pmdac: dac power management 0: power-down (default) 1: power-up pmspk: speaker-amp power management 0: power-down (default) 1: power-up pmmin: min input power management 0: power-down (default) 1: power-up the pmmin bit must be set to ?1? at the same time when the pmhpl bit, pmhpr bit or pmspk bit is set to ?1?. pmvcm: vcom power management 0: power-down (default) 1: power-up when any blocks are powered-up, the pmvcm bit must be set to ?1?. the pmvcm b it can be set to ?0? only when all power management bits of 00h, 01h and mcko bits are ?0?. each block can be powered-down respectivel y by writing ?0? in each bit of this a ddress. when the pdn pin is ?l?, all blocks are powered-down regardless of the setting of this address. in this case, register is initialized to the default value. when all power management bits are ?0? in the 00h, 01h addresses and mcko bit is ?0?, all blocks are powered-down. the register values remain unchanged. the register values remain unc hanged. power supply current is 20 a(typ) in this case. for fully shut down (typ. 1 a), pdn pin must be ?l?. when dac is not used, external clocks may not be presen t. when dac is used, external clocks must always be present.
[ak4373] ms0991-e-00 2008/09 - 74 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 0 hpmtn p mhpl pmhpr m/s mckac mcko pmpll default 0 0 0 0 0 0 0 0 pmpll: pll power management 0: ext mode and power-down (default) 1: pll mode and power-up mcko: master clock output enable on all clock mode (pll master/slave mode1, 2 /ext master, slave mode) 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. mckac: mcki input mode select 0: cmos input (default) 1: ac coupling input m/s: master / slave mode select 0: slave mode (default) 1: master mode pmhpr: headphone-amp rch power management 0: power-down (default) 1: power-up pmhpl: headphone-amp lch power management 0: power-down (default) 1: power-up hpmtn: headphone-amp mute control 0: mute (default) 1: normal operation
[ak4373] ms0991-e-00 2008/09 - 75 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 sppsn mins dacs 0 hpbtl 0 pseudo 0 default 0 0 0 0 0 0 0 0 pseudo, hpbtl: headphone output type select hpbtl bit pseudo bit headphone output type figure table 0 0 single-ended (default) figure 1 table 35 1 0 differential figure 2 table 36 0 1 pseudo cap-less figure 3 table 37 1 1 n/a table 46. headphone output type select (n/a: not available) dacs: switch control from dac to speaker-amp 0: off (default) 1: on when dacs bit is ?1?, dac output signal is input to speaker-amp. mins: switch control from min to speaker-amp 0: off (default) 1: on when mins bit is ?1?, monaural signal is input to speaker-amp. sppsn: speaker-amp power-save mode 0: power-save mode (default) 1: normal operation when sppsn bit is ?0?, speaker-amp is in power-save mode. in this mode, the spp pin goes to hi-z and the spn pin is outputs hvdd/2 voltage. when pm spk bit = ?1?, sppsn bit is enabled. addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 0 0 0 spkg1 spkg0 0 0 0 default 0 0 0 0 0 0 0 0 spkg1-0: speaker-amp output gain select ( table 42 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll3 pll2 pll1 pll0 bcko dif2 dif1 dif0 default 0 0 0 0 0 0 1 0 dif2-0: audio interface format ( table 17 ) default: ?010? (left justified) bcko: bick output frequency select at master mode ( table 11 ) pll3-0: pll reference clock select ( table 5 ) default: ?0000? (lrck pin)
[ak4373] ms0991-e-00 2008/09 - 76 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 ps1 ps0 fs3 msbs bckp fs2 fs1 fs0 default 0 0 0 0 0 0 0 0 fs3-0: sampling frequency select ( table 6 and table 7 .) and mcki frequency select ( table 12 .) fs3-0 bits select sampling frequency at p ll mode and mcki frequency at ext mode. bckp: bick polarity at dsp mode ( table 18 ) ?0?: sdto is output by the rising edge (? ?) of bick and sdti is latched by the falling edge (? ?). (default) ?1?: sdto is output by the falling edge (? ?) of bick and sdti is latched by the rising edge (? ?). msbs: lrck polarity at dsp mode ( table 18 ) ?0?: the rising edge (? ?) of lrck is half clock of bick before the channel change. (default) ?1?: the rising edge (? ?) of lrck is one clock of bick before the channel change. ps1-0: mcko output frequency select ( table 10 ) default: ?00? (256fs)
[ak4373] ms0991-e-00 2008/09 - 77 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select dvtm wtm2 ztm 1 ztm0 wtm1 wtm0 rfst1 rfst0 default 0 0 0 0 0 0 0 0 rfst1-0: alc first recovery speed ( table 28 ) default: ?00?(4times) wtm2-0: alc recovery waiting period ( table 25 .) default: ?000? (128/fs) ztm1-0: alc limiter/recovery operation zero crossing timeout period ( table 24 .) default: ?00? (128/fs) dvtm: digital volume transition time setting ( table 33 .) 0: 1061/fs (default) 1: 256/fs this is the transition time between dvl/r7-0 bits = 00h and ffh. addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection level / recovery counter reset level ( table 22 .) default: ?00? lmth1 bit is d6 bit of 0bh. rgain1-0: alc recovery gain step ( table 26 .) default: ?00? rgain1 bit is d7 bit of 0bh. lmat1-0: alc limiter att step ( table 23 .) default: ?00? zelmn: zero crossing detection en able at alc limiter operation 0: enable (default) 1: disable alc: alc enable 0: alc disable (default) 1: alc enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref7-0: reference value at alc recovery operation. 0.375db step, 242 level ( table 27 .) default: ?e1h? (+30.0db)
[ak4373] ms0991-e-00 2008/09 - 78 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h lch input volume control avl7 avl6 avl5 avl4 avl3 avl2 avl1 avl0 0ch rch input volume control avr7 avr6 avr5 avr4 avr3 avr2 avr1 avr0 default 1 1 1 0 0 0 0 1 avl7-0, avr7-0: alc block digital volume; 0.375db step, 242 level ( table 30 .) default:?e1h? (+30db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 default 0 0 0 1 1 0 0 0 dvl7-0, dvr7-0: output digital volume ( table 32 .) default: ?18h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc mode control 3 rgain1 lmth1 0 0 0 frn vbat 0 default 0 0 0 0 0 0 0 0 vbat: hp-amp common voltage ( table 40 .) 0: 0.5 x hvdd (default) 1: 0.64 x avdd frn: fast recovery enable 0: enable(default) 1:disable lmth1: alc limiter detection level / recovery counter reset level ( table 22 .) rgain1: alc recovery gain step ( table 26 .) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh mode control 3 0 0 smute dvolc 0 0 dem1 dem0 default 0 0 0 1 0 0 0 1 dem1-0: de-emphasis frequency select ( table 31 ) default: ?01? (off) dvolc: output digital volu me control mode select 0: independent 1: dependent (default) when dvolc bit = ?1?, dvl7-0 bits control both lch and rch volume level, while register values of dvl7-0 bits are not written to dvr7-0 bits. when dvol c bit = ?0?, dvl7-0 bits control lch level and dvr7-0 bits control rch level, respectively. smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted
[ak4373] ms0991-e-00 2008/09 - 79 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh mode control 4 0 0 0 0 avolc hpm minh dach default 0 0 0 0 1 0 0 0 dach: switch control from dac to headphone-amp 0: off (default) 1: on minh: switch control from min to hp-amp 0: off (default) 1: on when minh bit is ?1?, monaural signal is input to hp-amp. hpm: headphone-amp mono output select 0: stereo (default) 1: mono when the hpm bit = ?1?, dac output signal is output to lch and rch of the headphone-amp as (l+r)/2. hpm bit must be changed when dac is powered-down. avolc: alc block digital vo lume control mode select 0: independent 1: dependent (dfault) when avolc bit = ?1?, avl7-0 bits control both lch and rch volume level, while register values of avl7-0 bits are not written to avr7-0 bits. when avol c bit = ?0?, avl7-0 bits control lch level and avr7-0 bits control rch level, respectively. addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 3 0 0 hpg 0 0 0 0 0 default 0 0 0 0 0 0 0 0 hpg: headphone-amp gain select ( table 38 .) 0: 0db (default) 1: +3.6db hpg bit must be changed when the headphone-amp is powered-down. addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h digital filter select 1 gn1 gn0 lpf hpf eq fil3 0 0 default 0 0 0 0 0 0 0 0 fil3: fil3 (stereo separation emphasis filter) coefficient setting enable 0: disable (default) 1: enable when fil3 bit is ?1?, the settings of f3a13-0 and f3b13- 0 bits are valid. when fil3 bit is ?0?, fil3 block is through (0db). eq: eq (gain compensation filter) coefficient setting enable 0: disable (default) 1: enable when eq bit is ?1?, the settings of eqa15-0, eqb13-0 and eqc15-0 bits are valid. when eq bit is ?0?, eq block is through (0db). hpf: high pass filter coefficient setting enable 0: disable (default) 1: enable when hpf bit is ?1?, the settings of f1a13-0 and f1b13-0 bits are valid. when hpf bit is ?0?, hpf block is through (0db).
[ak4373] ms0991-e-00 2008/09 - 80 - lpf: low pass filter coefficient setting enable 0: disable (default) 1: enable when lpf bit is ?1?, the settings of f2a13-0 and f2b13-0 bits are valid. when lpf bit is ?0?, lpf block is through (0db). gn1-0: gain select at gain block ( table 21 .) default: ?00?
[ak4373] ms0991-e-00 2008/09 - 81 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8 default 0 0 0 0 0 0 0 0 f3a13-0, f3b13-0: fil3 (stereo separati on emphasis filter) coefficient (14bit x 2) default: ?0000h? f3as: fil3 (stereo separation emphasis filter) select 0: hpf (default) 1: lpf eqa15-0, eqb13-0, eqc15-c0: eq (gain compen sation filter) coefficient (14bit x 2 + 16bit x 1) default: ?0000h? f1a13-0, f1b13-0: high pass filer coefficient (14bit x 2) default: ?0000h? f2a13-0, f2b13-0: low pass filer coefficient (14bit x 2) default: ? 0000h ?
[ak4373] ms0991-e-00 2008/09 - 82 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 r/w rd rd rd r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 eq1: equalizer 1 coefficient setting enable 0: disable (default) 1: enable when eq1 bit is ?1?, the settings of e1a15-0, e1b15-0 and e1c15-0 bits are enable d. when eq1 bit is ?0?, eq1 block is through (0db). eq2: equalizer 2 coefficient setting enable 0: disable (default) 1: enable when eq2 bit is ?1?, the settings of e2a15-0, e2b15-0 and e2c15-0 bits are enable d. when eq2 bit is ?0?, eq2 block is through (0db). eq3: equalizer 3 coefficient setting enable 0: disable (default) 1: enable when eq3 bit is ?1?, the settings of e3a15-0, e3b15-0 and e3c15-0 bits are enable d. when eq3 bit is ?0?, eq3 block is through (0db). eq4: equalizer 4 coefficient setting enable 0: disable (default) 1: enable when eq4 bit is ?1?, the settings of e4a15-0, e4b15-0 and e4c15-0 bits are enable d. when eq4 bit is ?0?, eq4 block is through (0db). eq5: equalizer 5 coefficient setting enable 0: disable (default) 1: enable when eq5 bit is ?1?, the settings of e5a15-0, e5b15-0 and e5c15-0 bits are enable d. when eq5 bit is ?0?, eq5 block is through (0db).
[ak4373] ms0991-e-00 2008/09 - 83 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 e1a15-0, e1b15-0, e1c15-0: equalizer 1 coefficient (16bit x3) default: ? 0000h ? e2a15-0, e2b15-0, e2c15-0: equalizer 2 coefficient (16bit x3) default: ? 0000h ? e3a15-0, e3b15-0, e3c15-0: equalizer 3 coefficient (16bit x3) default: ? 0000h ? e4a15-0, e4b15-0, e4c15-0: equalizer 4 coefficient (16bit x3) default: ? 0000h ? e5a15-0, e5b15-0, e5c15-0: equalizer 5 coefficient (16bit x3) default: ? 0000h ?
[ak4373] ms0991-e-00 2008/09 - 84 - system design figure 68, figure 69 and figure 70 shows the system connection diagram for the ak4373. the evaluation board [AKD4373] demonstrates the optimum layout, power supply arrangements and measurement results. [headphone: single-ended mode] mutet rout lo ut min+ min - n c n c n c hpl/hpl+ h p r/ hp l- v ss2 hvdd spp/hpr+/test spn/hpr-/hvcm mcko mcki nc vco m v ss1 a vdd vcoc i2c pdn csn vs s3 dvdd bi ck lrck nc sdti cdti cclk a k4373en top view 2 5 2 6 27 2 8 29 30 3 1 3 2 24 23 2 2 1 1 6 1 5 14 13 1 2 11 1 0 9 21 20 19 18 17 2 3 4 5 6 7 8 1u 0.1u 2.2u 0 .1u rp 220u 220u power supply 2.2 3.6v 0 .1u 0.1u 10 ds p p headphone sp ea ker cp 10u analog ground digital ground zd 2 zd1 dyn amic spk r1 , r2 : s ho r t z d1, zd 2: o pe n pie zo spk r1 , r2 : 10 z d1, zd 2: r equ ired r1 r 2 mo no in line ou t 1u 1u ri ri notes: - vss1, vss2 and vss3 of the ak4373 must be distributed separately from the ground of external controllers. - all digital input pins should not be left floating. - when the ak4373 is ext mode (pmpll bit = ?0?), a resistor and a capacitor of the vcoc pin are not needed. - when the ak4373 is pll mode (pmpll bit = ?1?), a resistor and a capacitor of the vcoc pin are shown in table 5 . - when piezo speaker is used, 2.6 4.0v power must be supplied to hvdd and 20 or more series resistors must be connected to both spp and spn pins, respectively. - when the ak4373 is used at master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, 100k around pull-up resistor must be connected to lrck and bick pins of the ak4373. - if the analog mixing block is used as a single-ended, the min- pin must be connected to vss1 in series with a capacitor to avoid induced external noise. figure 68. typical connection diagram (single-ended mode, hpbtl bit = pseudo bit = ?0?)
[ak4373] ms0991-e-00 2008/09 - 85 - [headphone: differential mode] mutet rout lo ut min+ min - n c n c n c v ss2 hvdd mcko mcki nc vco m v ss1 a vdd vco c i2c pdn csn vs s3 dvdd bi ck lrck nc sdti cdti cclk a k4373en top view 2 5 2 6 27 2 8 29 30 3 1 3 2 24 23 22 1 1 6 1 5 14 13 1 2 11 1 0 9 21 20 19 18 17 2 3 4 5 6 7 8 1u 0.1u 2.2u 0.1u rp power supply 2.2 3.6v 0 .1u 0.1u 10 ds p p he ad pho ne rch cp 10u analog ground digital ground headphone lch hpl/hpl+ h p r/ hp l- spp/hpr+/test spn/hpr-/hvcm mo no in ri ri notes: - vss1, vss2 and vss3 of the ak4373 must be distributed separately from the ground of external controllers. - all digital input pins must not be left floating. - when the ak4373 is ext mode (pmpll bit = ?0?), a resistor and a capacitor of the vcoc pin are not needed. - when the ak4373 is pll mode (pmpll bit = ?1?), a resistor and a capacitor of the vcoc pin are shown in table 5 . - when the ak4373 is used at master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, 100k around pull-up resistor must be connected to lrck and bick pins of the ak4373. - if the analog mixing block will is used as a single-ended, the min- pin must be connected to vss1 in series with a capacitor to avoid induced external noise. figure 69. typical connection di agram (differential mode, hpb tl bit = ?1?, pseudo bit = ?0?)
[ak4373] ms0991-e-00 2008/09 - 86 - [headphone: pseudo cap-less mode] mu tet rou t lout mi n+ mi n- nc nc nc hpl/hpl+ hpr/hpl- vss2 hvdd s pp / hpr+ / te s t spn/hpr-/hvcm mc ko mc ki n c vcom vss 1 a vdd vcoc i2 c pdn csn vss3 dvdd bick lrck n c sdti cdti cclk a k4373en top view 2 5 26 27 28 29 30 31 3 2 24 23 22 1 1 6 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 1u 0.1u 2.2u 0.1u rp power supply 2.2 3.6v 0.1u 0.1u 10 dsp p cp 10u analog ground digital ground mono in ri ri headphone notes: - vss1, vss2 and vss3 of the ak4373 must be distributed separately from the ground of external controllers. - all digital input pins must not be left floating. - when the ak4373 is ext mode (pmpll bit = ?0?), a resistor and a capacitor of the vcoc pin are not needed. - when the ak4373 is pll mode (pmpll bit = ?1?), a resistor and a capacitor of the vcoc pin are shown in table 5 . - when the ak4373 is used at master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, 100k around pull-up resistor must be connected to lrck and bick pins of the ak4373. - if the analog mixing block is used as a single-ended, the min- pin must be connected to vss1 in series with a capacitor to avoid induced external noise. figure 70. typical connection diagram (pseudo cap-less mode, hpbtl bit = ?0?, pseudo bit = ?1?)
[ak4373] ms0991-e-00 2008/09 - 87 - 1. grounding and power supply decoupling the ak4373 requires careful attention to power s upply and grounding arrangements. avdd, dvdd and hvdd are usually supplied from the system?s analog supply. if avdd, dvdd and hvdd are supplied separately, the power-up sequence is not critical. vss1, vss2 and vss3 of the ak4373 must be connected to the analog ground plane. system analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors must be as close to the ak4373 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak4373. 3. analog outputs the input data format for the dac is 2?s comple ment. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the line ou tput-amp, headphone-amp and speaker-amp outputs are centered at hvdd/2 when vbat bit is ?0?. ( table 40 )
[ak4373] ms0991-e-00 2008/09 - 88 - control sequence clock set up when dac is powered-up, the clocks must be supplied. 1. pll master mode. bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) 40msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input m/s bit (addr:01h, d3) mcko pin output (8) (7) 40msec(max) example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:01h, data:08h addr:04h, data:4ah addr:05h, data:27h (4)addr:01h, data:0bh mcko, bick and lrck output figure 71. clock set up sequence (1) (1) after power up, pdn pin = ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4373. (2) dif1-0, pll3-0, fs3-0, bcko and m/s bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom must first be powered-up before the other block operates. (4) in case of using mcko output: mcko bit = ?1? in case of not using mcko output: mcko bit = ?0? (5) pll lock time is 40ms(max) after pmpll bit changes fro m ?0? to ?1? and mcki is supplied from an external source. (6) the ak4373 starts to output the lrck and the bick clocks after the pll becomes stable. then normal operation starts. (7) the invalid frequency is output from the mcko pin during this period if mcko bit = ?1?. (8) the normal clock is output from the mcko pin after the pll is locked if mcko bit = ?1?.
[ak4373] ms0991-e-00 2008/09 - 89 - 2. pll slave mode (lrck or bick pin) pmpll bit (addr:01h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) (5) input 4fs of example: audio i/f format : msb justified pll reference clock: bick bick frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:32h addr:05h, data:27h (4) addr:01h, data:01h figure 72. clock set up sequence (2) (2) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4373. (3) dif1-0, fs3-0 and pll3-0 bits should be set during this period. (4) power up vcom: pmvcm bit = ?0? ? ?1? vcom must first be powered up before the other block operates. (5) pll starts after the pmpll bit cha nges from ?0? to ?1? and pll reference clock (lrck or bick pin) is supplied. pll lock time is 160ms(max) when lrck is a pll reference clock. and pll lock time is 4ms(max) when bick is a pll reference clock. (6) normal operation stats after that the pll is locked.
[ak4373] ms0991-e-00 2008/09 - 90 - 3. pll slave mode (mcki pin) bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 40msec(max) (8) input example: audio i/f format: msb justified input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:04h, data:4ah addr:05h, data:27h (4)addr:01h, data:03h mcko output start bick and lrck input start figure 73. clock set up sequence (3) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4373. (2) dif1-0, pll3-0 and fs3-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom must first be powered up before the other block operates. (4) enable mcko output: mcko bit = ?1? (5) pll starts after that the pmpll b it changes from ?0? to ?1? and pll reference clock (mcki pin) is supplied. pll lock time is 40ms(max). (6) the normal clock is output from mcko after pll is locked. (7) the invalid frequency is output from mcko during this period. (8) bick and lrck clocks should be synchronized with mcko clock.
[ak4373] ms0991-e-00 2008/09 - 91 - 4. ext slave mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) input (4) mcki pin input example: audio i/f format: msb justified input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:02h addr:05h, data:00h mcki, bick and lrck input figure 74. clock set up sequence (4) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4373. (2) dif1-0 and fs1-0 bits must be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom must first be powered up before the other block operates. (4) normal operation starts after the mcki, lrck and bick are supplied.
[ak4373] ms0991-e-00 2008/09 - 92 - 5. ext master mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (3) (4) lrck pin bick pin (2) mcki pin input m/s bit (addr:01h, d3) output example: audio i/f format: msb justified input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (4) addr:00h, data:40h (3) addr:04h, data:02h addr:05h, data:00h addr:01h, data:08h bick and lrck output (2) mcki input figure 75. clock set up sequence (5) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4373. (2) mcki must be input. (3) after dif1-0 and fs1-0 bits are set, m/s bit should be set to ?1?. then lrck and bick are output. (4) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates.
[ak4373] ms0991-e-00 2008/09 - 93 - speaker-amp output fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmspk bit (addr:00h, d4) 1,111 0,000 18h 28h spp pin normal output sppsn bit (addr:02h, d7) hi-z hi-z spn pin normal output hvdd/2 hvdd/2 (1) (9) 1 0 (7) alc bit (addr:07h, d5) (10) (11) (14) (12) dacs bit (addr:02h, d5) (13) 01 00 (3) spkg1-0 bits (addr:03h, d4-3) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (8) (2) (6) alc control 1 (addr:06h) 00h 3ch (4) alc control 2 (addr:08h) e1h c1h (5) alc control 3 (addr:0bh) 00h 00h pmmin bit (addr:00h, d5) example: pll master mode audio i/f format: msb justified sampling frequency: 44.1khz digital volume: ? 8db alc: enable (2) addr:02h, data:20h (7) addr:07h, data:20h (1) addr:05h, data:27h (9) addr:0ah & 0dh, data:28h (10) addr:00h, data:74h (11) addr:02h, data:a0h (12) addr:02h, data:20h playback (13) addr:02h, data:00h (14) addr:00h, data:40h (3) addr:03h, data:08h (8) addr:09h & 0ch, data:91h (4) addr:06h, data:3ch (5) addr:08h, data:e1h (6) addr:0bh, data:00h figure 76. speaker-amp output sequence at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4373 is pll mode, dac and speaker-amp should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of ?dac ? spk-amp?: dacs bit = ?0? ? ?1? (3) spk-amp gain setting: spkg1-0 bits = ?00? ? ?01? (4) set up timer select for alc (addr: 06h) (5) set up ref value for alc (addr: 08h) (6) set up lmth1 and rgain1 bits (addr: 0bh) (7) set up lmth0, rgain0, lmat1-0 and alc bits (addr: 07h) (8) set up the alc block digital volume (addr: 09h and 0ch) avl7-0 and avr7-0 bits should be set to ?91h?(0db). (9) set up the output digital volume (addr: 0ah and 0dh). when dvolc bit is ?1? (default), dvl7- 0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (10) power up of dac and speaker-amp: pmdac = pmspk bits = ?0? ?1? when alc bit is ?1?, alc operation starts from the gain set by avl/r7-0 bits. (11) exit the power-save-mode of speaker-amp: sppsn bit = ?0? ?1? (12) enter the power-save-mode of speaker-amp: sppsn bit = ?1? ?0? (13) disable the path of ?dac ? spk-amp?: dacs bit = ?1? ? ?0? (14) power down dac and speaker-amp: pmdac = pmspk bits = ?1? ?0?
[ak4373] ms0991-e-00 2008/09 - 94 - headphone-amp output (single-ended or differential or pseudo cap-less) fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmhpl/r bits (addr:01h, d5-4) hpmtn bit (addr:01h, d6) hpl/r pins hpl+/- pins hpr+/- pins hvcm pin 1,111 0,000 18h 28h normal output (1) hpbtl,pseu do bits (addr:02h, d3,d1) "0" "00"(single-ended)/ "10"(full- differential)/ "01"(pseudo cap-less) (3) (5) pmdac bit (addr:00h, d2) (6) (11) (7) (9) (8) (10) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (4) pmmin bit (addr:00h, d5) dach bit (addr:0fh, d0) (2) (12) example: pll, master mode audio i/f format :msb justified sampling frequency: 44.1khz digital volume: ? 8db bass b oost level : middle (1) addr:05h, data:27h (2) addr:0fh, data:09h (4) addr:09h&0ch, data:91h (5) addr:0ah&0dh, data:28h (6) addr:00h, data:64h (7) addr:01h, data:39h (8) addr:01h, data:79h playback (9) addr:01h, data:39h (10) addr:01h, data:09h (11) addr:00h, data:40h (3) addr:02h, data:00h/08h/02h (12) addr:0f h, data:08h figure 77. headphone-amp output sequence at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4373 is pll mode, dac and speaker-amp should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of ?dac hp-amp?: dach bit = ?0? ?1? (3) select output type of the headphone (hpbtl and pse udo bits ?00?= single-ended, ?10?=differential, ?01?=pseudo cap-less) (4) set up the alc block digital volume (addr: 09h and 0ch) avl7-0 and avr7-0 bits should be set to ?91h?(0db). (5) set up the output digital volume (addr: 0ah and 0dh) when dvolc bit is ?1? (default), dvl 7-0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (6) power up dac: pmdac bit = ?0? ?1? when alc bit is ?1?, alc operation starts from the gain set by avl/r7-0 bits. (7) power up headphone-amp: pmhpl = pmhpr bits = ?0? ?1? output voltage of headphone-amp is still vss2. (8) rise up the common voltage of headphone-amp: hpmtn bit = ?0? ?1? the rise time depends on hvdd and the capacitor valu e which connected with the mutet pin. when hvdd=3.3v and the capacitor value is 1.0 f, the time constant is r = 100ms(typ), 250ms(max). (9) fall down the common voltage of headphone-amp: hpmtn bit = ?1? ?0? the fall time depends on hvdd and the capacitor valu e which connected with the mutet pin. when hvdd=3.3v and the capacitor value is 1.0 f, the time constant is f = 100ms(typ), 250ms(max). if the power supply is powered-off or headphone-amp is powered-down before the common voltage changes to gnd, the pop noise occurs. it takes twice of f that the common voltage changes to gnd. (10) power down headphone-amp: pmhpl = pmhpr bits = ?1? ?0? (11) power down dac: pmdac bit = ?1? ?0? (12) disable the path of ?dac hp-amp?: dach bit = ?1? ?0?
[ak4373] ms0991-e-00 2008/09 - 95 - stop of clock master clock can be stopped when dac is not used. 1. pll master mode external mcki pmpll bit (addr:01h, d0) mcko bit (addr:01h, d1) input (3) (1) (2) "1" or "0" example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz (3) stop an external mcki (1) (2) addr:01h, data:08h figure 78. clock stopping sequence (1) (1) power down pll: pmpll bit = ?1? ?0? (2) stop mcko clock: mcko bit = ?1? ?0? (3) stop an external master clock. 2. pll slave mode (lrck or bick pin) external bick pmpll bit (addr:01h, d0) input (1) (2) external lrck input (2) example audio i/f format : msb justified pll reference clock: bick bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 79. clock stopping sequence (2) (1) power down pll: pmpll bit = ?1? ?0? (2) stop the external bick and lrck clocks 3. pll slave (mcki pin) external mcki pmpll bit (addr:01h, d0) input (1) (2) mcko bit (addr:01h, d1) (1) example audio i/f format: msb justified pll reference clock: mcki bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 80. clock stopping sequence (3) (1) power down pll: pmpll bit = ?1? ?0? stop mcko output: mcko bit = ?1? ?0? (2) stop the external master clock.
[ak4373] ms0991-e-00 2008/09 - 96 - 4. ext slave mode external lrck input (1) external bick input (1) external mcki input (1) example audio i/f format :msb justified input mcki frequency:1024fs (1) stop the external clocks figure 81. clock stopping sequence (4) (1) stop the external mcki, bick and lrck clocks. 5. ext master mode lrck output bick output external mcki input (1) "h" or "l" "h" or "l" example audio i/f format :msb justified input mcki frequency:1024fs (1) stop the external mcki figure 82. clock stopping sequence (5) (1) stop mcki clock. bick and lrck are fixed to ?h? or ?l?. power supply current can also be shut down (typ. 1 a) by stopping clocks and setting pdn pin = ?l?. when pdn pin = ?l?, the registers are initialized.
[ak4373] ms0991-e-00 2008/09 - 97 - package 32pin qfn (unit: mm) 4.75 0.10 5.00 0.10 4.75 0.10 0.50 0.23 24 17 25 1 16 1 0.01 0.08 32 8 9 c0.42 32 +0.07 -0.05 0.40 0.10 0.20 + 0.04 - 0.01 c exposed pad 3.5 5.00 0.10 0.85 0.05 c b a 0.10 m ab 3.5 note) the exposed pad on the bottom surface of the p ackage must be open or connected to the ground. material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[ak4373] ms0991-e-00 2008/09 - 98 - marking a k4373 x xxx x 1 a km xxxxx : date code identifier (5 digits) revision history date (yy/mm/dd) revision reason page contents 08/09/09 00 first edition important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

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